Veripool

Today

02:41 am Verilator Issue #648 (Assigned): Error-BLKANDNBLK with nested modules in generate block

I'm not immediately sure how to fix this. The conflict is at that port since a single bit is selected that is effect... Wilson Snyder

02:11 am Verilog-mode Issue #562: bus width alignment

BTW to find the logic around this in the sources, look for verilog-auto-lineup. I would suggest adding an additional... Wilson Snyder

12:31 am Verilator Issue #649 (Feature): support for streaming operators

I don't personally have a huge interest in this as it's uncommon syntax, but if you or someone else would like to tak... Wilson Snyder

05/21/2013

11:58 pm Verilator Issue #649 (Feature): support for streaming operators

This is more a feature request rather than bug. Today SV's {<<{...}} and {>>{...}} operators generate syntax error, s... Krzysztof Jankowski

11:52 pm Verilator Issue #645 (Resolved): VL_INW and VL_OUTW macros require 4 arguments, but only 3 given

Wilson Snyder

11:50 pm Verilator Issue #645: VL_INW and VL_OUTW macros require 4 arguments, but only 3 given

It seems to be working now. Thanks for the quick fix! Krzysztof Jankowski

11:48 pm Verilator Issue #648 (Assigned): Error-BLKANDNBLK with nested modules in generate block

The attached code gives error: ??%Error-BLKANDNBLK: condgen.sv:29: Unsupported: Blocked and non-blocking assignments ... Krzysztof Jankowski

09:38 pm Verilog-Perl Issue #641 (Closed): SigParser and DPI function callbacks

In 3.401.
Wilson Snyder

09:38 pm Verilog-Perl Issue #627 (Closed): SigParser parse_file results in syntax error, unexpected ::, expecting "'{"

In 3.401.
Wilson Snyder

09:38 pm Verilog-Perl Verilog-Perl 3.401 Released

Verilog::Language 3.401 2013-05-21
*** Fix recognizing type parameters as classes, bug627. [Jon Nall]
**** Fix ... Wilson Snyder

07:24 pm Verilog-mode Issue #647 (New): verilog-read-defines issue with multiline comments

I am seeing defines being set if they are in a multiline comment. See the following example.
module test (/*AUTOA... Michael Rytting

06:14 pm Verilog-Perl Issue #641: SigParser and DPI function callbacks

Wilson,
Any ETA on this release?
Thanks,
nall. Jon Nall

05/19/2013

02:00 pm Verilator Issue #646 (AskedReporter): Asignments of arithmetic operations embedded in a concatenation cause...

Your example is not valid verilog, you can't have a constant on the left hand side. If you could modify the attached... Wilson Snyder

09:59 am Verilator Issue #646 (AskedReporter): Asignments of arithmetic operations embedded in a concatenation cause...

Trying to use a single wire concatenated with a vector to capture an addition overflow was causing a mismatch between... Daniel Bone

12:18 am Verilator Issue #645: VL_INW and VL_OUTW macros require 4 arguments, but only 3 given

Ok, please try the latest git, thanks for the test.
Wilson Snyder

05/18/2013

12:03 am Verilator Issue #645: VL_INW and VL_OUTW macros require 4 arguments, but only 3 given

Attached files try to demonstrate the problem. Compilation with verilator v3.847 gives the original problem. When com... Krzysztof Jankowski

05/17/2013

10:47 am Verilator Issue #645: VL_INW and VL_OUTW macros require 4 arguments, but only 3 given

I need a test case please.
Wilson Snyder

03:25 am Verilator Issue #645: VL_INW and VL_OUTW macros require 4 arguments, but only 3 given

This time my signals were declared in C++ headers like below:... Krzysztof Jankowski

05/16/2013

02:02 am Verilator Issue #645 (AskedReporter): VL_INW and VL_OUTW macros require 4 arguments, but only 3 given

I tried a couple of things to make a test case and am missing something. But the code is obvious how to fix given yo... Wilson Snyder

05/14/2013

06:38 am Verilator Issue #645: VL_INW and VL_OUTW macros require 4 arguments, but only 3 given

Here is the exact SV port declaration with corresponding auto-generated C++ function:... Krzysztof Jankowski

12:25 am Verilator Issue #645: VL_INW and VL_OUTW macros require 4 arguments, but only 3 given

I see how the code could do that, it's a bug, but I don't know what the test case is; how is arr_inp_dat declared? Wilson Snyder

12:03 am Verilator Issue #645 (Resolved): VL_INW and VL_OUTW macros require 4 arguments, but only 3 given

I'm getting below errors while compiling C++ code generated by verilator v3.847:... Krzysztof Jankowski

05/12/2013

12:03 pm Verilog-mode Issue #644 (NoFixNeeded): AUTOINST uses parameter names in enclosing module, which often produces...

Wilson Snyder

05/11/2013

09:26 pm Verilog-mode Issue #644: AUTOINST uses parameter names in enclosing module, which often produces errors

Yep, that looks exactly like what I was looking for. Thanks! Jeff Bush

08:22 pm Verilog-mode Issue #644 (AskedReporter): AUTOINST uses parameter names in enclosing module, which often produc...

Please look at the documentation for verilog-auto-inst-param-value and let me know if that does what you want.
Wilson Snyder

08:18 pm Verilator Issue #642 (Closed): generate problems with non-zero min index array

In 3.847.
Wilson Snyder

08:17 pm Verilator Patch #638 (Closed): Support for sc_uint, sc_biguint

In 3.847.
Wilson Snyder

08:17 pm Verilator Issue #643 (Closed): random crash with nested sv structs

In 3.847.
Wilson Snyder

08:17 pm Verilator Issue #631 (Closed): Verilator mis-searches for modules with double underscores with __05F

In 3.847.
Wilson Snyder

08:17 pm Verilator Issue #634 (Closed): Incorrect simulation in presence of MULTIDRIVEN

In 3.847.
Wilson Snyder

08:16 pm Verilator Patch #638: Support for sc_uint, sc_biguint

In 3.847.
Wilson Snyder

08:15 pm Verilator Verilator 3.847 Released

Verilator 3.847 2013-05-11
*** Add ALWCOMBORDER warning. [KC Buckenmaier]
*** Add --pins-sc-uint and --pin... Wilson Snyder

06:28 pm Verilog-mode Issue #644 (NoFixNeeded): AUTOINST uses parameter names in enclosing module, which often produces...

Assume we create a module as follows:... Jeff Bush

01:00 am Verilator Issue #643 (Resolved): random crash with nested sv structs

Good example again. Wish I could say this will be the last, but struct/unions need more real world testing.
Fixed... Wilson Snyder

12:17 am Verilator Issue #643 (Closed): random crash with nested sv structs

Attached sv file contains various packed structs and it crashes with random error messages, sometimes it even compile... Krzysztof Jankowski

05/10/2013

11:10 am Verilator Issue #642 (Resolved): generate problems with non-zero min index array

Good example. Simple enough, fixed in git towards 3.847.
Wilson Snyder

03:34 am Verilator Issue #642 (Closed): generate problems with non-zero min index array

... Krzysztof Jankowski

05/06/2013

10:44 pm Verilog-Perl Issue #641: SigParser and DPI function callbacks

I'm not currently aware of any other issues. I'd say go ahead and push 3.401 when you're ready. Jon Nall

05/04/2013

07:50 pm Verilog-Perl Issue #641 (Resolved): SigParser and DPI function callbacks

Indeed. Added end callbacks for task/function DPIs and also class methods.
Pushed to git towards 3.401. If this w... Wilson Snyder

05/03/2013

06:58 pm Verilog-Perl Issue #641 (Closed): SigParser and DPI function callbacks

Consider this verilog:... Jon Nall

05/02/2013

06:44 pm Verilator Issue #634: Incorrect simulation in presence of MULTIDRIVEN

Confirmed master branch passes my full design. Thanks Wilson. Ted Campbell

12:27 pm Verilator Issue #634 (Resolved): Incorrect simulation in presence of MULTIDRIVEN

Thanks for the good debugging and patches. I had tried the patch on larger designs and ran out of memory, so while t... Wilson Snyder

05/01/2013

05:23 pm Verilog-mode Issue #640 (WillNotFix): AUTOINST truncates inputs with array instantiation and wide inputs

Right, it doesn't look at the array subscripting, not do I plan on changing this in the near term. Sorry it caused c... Wilson Snyder

02:09 am Verilog-mode Issue #640 (WillNotFix): AUTOINST truncates inputs with array instantiation and wide inputs

I'm not sure what the right behavior is here, or if this is even something that should be handled automatically, but ... Jeff Bush

04/30/2013

12:57 pm Verilog-mode Issue #637 (Closed): Array ports are not handled properly by AUTOINST

This should be fixed in the latest release.
Wilson Snyder

04/29/2013

12:20 am Verilog-mode Issue #637 (Assigned): Array ports are not handled properly by AUTOINST

Hmm, yes. I have a simple fix that does OK, but there are other issues. Ideally some of the code should be refactor... Wilson Snyder

04/28/2013

01:04 pm Verilator Patch #639 (Closed): Small improvements to internals documentation

Good additions, pushed to git towards 3.847.
Wilson Snyder

12:42 pm Verilator Patch #639 (Closed): Small improvements to internals documentation

I have often found myself needing a reminder of how to configure a PERL test script. All this information is availabl... Jeremy Bennett

04/27/2013

01:03 am Verilator Patch #638 (Resolved): Support for sc_uint, sc_biguint

Thanks for the tests!
Pushed to git towards 3.847.
Wilson Snyder

04/25/2013

05:49 am Verilator Patch #638: Support for sc_uint, sc_biguint

Attached is a new patch that includes 3 tests (for sc-uint, sc-biguint and both together). Alex Hornung

04/24/2013

11:15 pm Verilator Patch #638 (Feature): Support for sc_uint, sc_biguint

Great, good job. I think we'll eventually end up needing a more generic way of specifying options as to what type to... Wilson Snyder

08:52 pm Verilator Patch #638 (Closed): Support for sc_uint, sc_biguint

Attached is a patch that implements generation of sc_uint for widths 2..64 and sc_biguint for widths 65..512 (indepen... Alex Hornung