Activity

From 02/13/2010 to 03/14/2010

12:37 pm Verilog-Perl Issue #222 (Resolved): An example in Verilog::EditFiles doesn't work: Fixed in git for next release, 3.232 Wilson Snyder
12:33 pm Verilog-Perl Issue #222 (Resolved): An example in Verilog::EditFiles doesn't work: Bug via RT
Thu Mar 11 01:45:25 2010: Request 55460 was acted upon.
Transaction: Ticket created by OutputLogic
... Wilson Snyder

05:04 pm Verilator Issue #220: Latch issue with clock gating signal: I will try to modify the previous one. You are right, there is a time zero behavior. Let me fix it and cross check to... Ashutosh Das
02:03 pm Verilator Issue #220: Latch issue with clock gating signal: There's two problems with the test you sent; first it relies on time zero behavior, it's better to make the same crc/... Wilson Snyder
01:54 am Verilator Issue #220: Latch issue with clock gating signal: Sorry for the delay, it took sometime to isolate the bug. What seems to be happening is that if we put clock_enable p... Ashutosh Das

11:51 am IPC::Locker IPC::Locker 1.485 Released: IPC::Locker 1.485 2010/03/04
**** Fix Pod::Usage dependency, rt51024. [Andreas Koenig]
Wilson Snyder

02:17 pm Verilog-Perl Issue #221 (Resolved): property errors: "disable iff" was mistakenly expecting an expression instead of a property_expression.
Fixed in git for next relea... Wilson Snyder
12:43 am Verilog-Perl Issue #221 (Resolved): property errors: when running latest release of verilog-perl on attached file, I get the following errors:
%Error: test20.v:9: synt... Rick Ramus

12:06 pm Verilator Issue #220: Latch issue with clock gating signal: P.S. See the docs about how to run this:
test_regress/t/t_clk_latchgate.pl --verbose
Wilson Snyder
12:02 pm Verilator Issue #220: Latch issue with clock gating signal: I made a self checking test and removed the pragmas, and
that seems to pass, so I also made it use more clocks (whic... Wilson Snyder

01:06 am Verilator Issue #217 (Resolved): Mac OS X build issues with 3.800: Found a system I could borrow.
Fixed in git for 3.801.
Wilson Snyder

11:56 pm Verilator Issue #220 (Assigned): Latch issue with clock gating signal: Wilson Snyder
11:55 pm Verilator Issue #219 (Closed): Issue related to clock gating signal with latch: Duplicate, see bug220.
Wilson Snyder
04:01 am Verilator Issue #219: Issue related to clock gating signal with latch: Please look at issue #220 which is the same as this one except much more readable. Thanks. Ashutosh Das
03:57 am Verilator Issue #220 (Assigned): Latch issue with clock gating signal: h3. Latch issue with clock gating
There seems to be an issue with the clock gating signal that prevents propagatio... Ashutosh Das
03:46 am Verilator Issue #219 (Closed): Issue related to clock gating signal with latch: There seems to be an issue with the clock gating signal that
prevents propagation of the signal through the flip-flo... Ashutosh Das
01:19 am SVN::S4 SVN::S4 1.033 Released: SVN::S4 1.033 2010/02/25
**** Fix Pod::Usage dependency, rt51024.
Wilson Snyder

12:32 am Vregs Vregs 1.464 Released: Vregs 1.464 2010/02/24
**** Fix Pod::Usage dependency, rt51024. [Andreas Koenig]
**** Fix GCC 4.3.2 comp... Wilson Snyder

12:35 pm Verilog-Perl Issue #202 (Closed): verilog parser error: In 3.231. Wilson Snyder
12:35 pm Verilog-Perl Verilog-Perl 3.231 Released: Verilog::Language 3.231 2010/02/21
**** Support 1800-2009 /*comments*/ in define values.
**** Fix DOS car... Wilson Snyder

02:04 pm Verilog-mode Issue #218 (New): pure virtual indentation: pure virtual functions indent wrong, because they don't have endfunctions (yuk, I know).... Wilson Snyder

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