Activity
From 08/05/2010 to 09/03/2010
08/29/2010
- 11:29 pm Verilator Issue #280 (Resolved): Can't trace signals with leading underscores.
- 11:28 pm Verilator Issue #280: Can't trace signals with leading underscores.
- Perfect! I forgot about coverage, glad you added that too.
Pushed to git for next release.
I may make tracing ... - 03:54 pm Verilator Issue #280: Can't trace signals with leading underscores.
- Patch attached, versus verilator_3_803
- 12:12 am Verilator Issue #280 (Assigned): Can't trace signals with leading underscores.
- Would you like to attempt adding an option, say -trace-underscore, yourself?
Search for "Leading Underscore" and t...
08/28/2010
- 04:10 pm Verilator Issue #280 (Resolved): Can't trace signals with leading underscores.
- I'm working with an existing (large) design that has a common idiom
of using an underscore ('_') prefix for wires/re...
08/26/2010
- 11:20 am Verilog-Perl Issue #266 (Rejected): vhier - ignore encrypted files
- Not a bug here.
- 11:19 am Verilog-Perl Patch #277 (Closed): Use Digest::SHA instead of Digest::SHA1
- In 3.302.
- 11:18 am Verilog-Perl Verilog-Perl 3.302 Released
- Verilog::Language 3.302 2010/08/26
**** Increase define recursions before error. [Paul Liu]
**** Fix doc...
08/18/2010
- 11:49 pm Verilog-mode Issue #279 (New): SystemVerilog Constraint auto-indentation
- When a constraint block contains foreach or if statements, auto-indent does not work...
- 11:40 pm Verilog-mode Issue #258 (Closed): "task automatic foo()" results in endcomment name "automatic"
- Fixed in revision 636
- 05:18 pm Rsvn rsvn 2.001 Created
- Rsvn a wrapper for subversion to greatly accelerate performance on NFS directories,
is now released as a Veripool pr... - 02:20 pm Verilog-mode Issue #259 (Closed): Wrong insertion of AUTOARG in Task
- Believed to be user setting.
- 02:19 pm Verilog-mode Issue #270 (Closed): AUTOINST and SystemVerilog interfaces
- Fixed in rev634.
Here's an example output; there may well be other issues as this is a fairly major change, let me... - 02:14 pm Verilog-mode Issue #264 (Closed): verilog-mode v616; single char signals not blue
- Sorry for the delay. Fixed in rev635.
08/16/2010
- 03:46 pm Verilog-Perl Issue #278 (Closed): verilog text does not print port direction for V2001 input code
- Ah, I see now the difference. You need to call $netlist->link after reading and before calling verilog_text as this ...
- 03:15 pm Verilog-Perl Issue #278 (Closed): verilog text does not print port direction for V2001 input code
- Reading in a Verilog 2001 file.. just the top level module (not its sub modules)
mod->dump shows that that ports a...
08/05/2010
- 05:40 pm Verilog-mode Issue #276 (Closed): Updating text from file on every C-c,C-a
- Glad it works.
- 05:36 pm Verilog-mode Issue #276: Updating text from file on every C-c,C-a
- Sorry for the confusion. I googled the issue and saw that someone else was having problems with this macro. I updated...
- 03:38 pm Verilog-Perl Patch #277 (Resolved): Use Digest::SHA instead of Digest::SHA1
- Fine patch, in git for next release.
- 03:32 pm Verilog-Perl Patch #277 (Closed): Use Digest::SHA instead of Digest::SHA1
- Hello,
The attached patch changes Verilog::Perl to use the Digest::SHA module instead of Digest::SHA1. Digest::SHA... - 03:18 pm Verilog-mode Issue #276: Updating text from file on every C-c,C-a
- Um, I'm confused, don't you want it to insert on every C-c C-a?
- 12:53 pm Verilog-mode Issue #276 (Closed): Updating text from file on every C-c,C-a
- My apologies if there is an easy way to do this already, but I couldn't find one, so I am adding this as a feature re...
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