Activity

From 01/07/2012 to 02/05/2012

02:35 am Verilog-mode Issue #386: Indenting of user-defined data types: BTW verilog-typedef-regexp if used needs to be specified as "\\w+_s\\>" or similar, since it needs to match in the mi... Wilson Snyder
02:32 am Verilog-mode Issue #386: Indenting of user-defined data types: I searched for "int" in verilog-mode.el and followed verilog-declaration-core-re to verilog-declaration-re. Adding t... Wilson Snyder
12:10 am Verilator Issue #304 (Closed): What can cause: Internal Error: Non-cutable edge forms a loop: This issue was resolved with a workaround. Wilson Snyder

02:38 pm Verilog-mode Issue #437 (New): Indentation of continued assignment incorrect if first line ends with ']': The indentation of an expression continued over multiple lines is incorrect when the first line of the expression end... Dan Dever

09:07 pm Verilog-mode Issue #435: Indenting comments on declarations in v736: Wilson,
Thanks for the quick reply, but in creating the test case I think I confused the issue. I am not concerne... Bruce LaVigne
08:46 pm Verilog-mode Issue #435: Indenting comments on declarations in v736: There's really two things here.
The first is the space between "input" and the signal name. This was changed in r... Wilson Snyder
08:14 pm Verilog-mode Issue #435 (New): Indenting comments on declarations in v736: I don't know when this stopped working, but in v736, comments on declaration lines no longer use comment-column:
<... Bruce LaVigne

11:27 pm Verilator Issue #434 (Closed): Small typo: Fixed for next release, thanks for the report.
Wilson Snyder
07:54 pm Verilator Issue #434 (Closed): Small typo: Hi,
Inside "test_sp/Makefile" there is:
@echo %Skip: SYSTERMPERL not in environment
should be:
@echo %Skip: SYS... Iztok Jeras

10:52 pm Verilog-mode Issue #433: indenting for some forms of SystemVerilog constraints is wrong/odd: wow. the html (or php?) code "displayer" really mangled that code. That's not at all what I pasted.
I'll try and... Brad Parker
10:50 pm Verilog-mode Issue #433 (New): indenting for some forms of SystemVerilog constraints is wrong/odd: indentation for several different forms of SV constraints is wrong or odd;
specifically, empty constraints are odd, ... Brad Parker
01:20 am Verilator Issue #432 (Resolved): Internal Error with large amount of UNOPTFLAT Warnings: No need for a test, I just reserved(1) and ran any test with the warning.
Fixed in git towards 3.832.
Wilson Snyder

08:48 pm Verilator Issue #432: Internal Error with large amount of UNOPTFLAT Warnings: oops, forgot to mention I originally saw this on 3.811 and got the same results with 3.831. Joe Eiler
08:46 pm Verilator Issue #432 (Resolved): Internal Error with large amount of UNOPTFLAT Warnings: I ran some code through verilator that caused an internal error, the code produces huge amounts of UNOPTFLAT warnings... Joe Eiler

12:11 pm Verilator Issue #414 (Closed): Instantiate per bit array of modules with sub-range as output: In 3.831.
Wilson Snyder
12:10 pm Verilator Patch #423 (Closed): DPI problem with > 32 bit but <= 64 bit args: In 3.831. Wilson Snyder
12:10 pm Verilator Verilator 3.831 Released: Verilator 3.831 2012/01/20
** Support SystemC 2.3.0 prerelease. This requires setting the new
SYSTEMC_I... Wilson Snyder
01:27 am SystemPerl SystemPerl 1.340 Released: SystemPerl 1.340 2012/01/19
*** Support SystemC 2.3.0 prerelease.
*** Support SYSTEMC_INCLUDE and SYSTE... Wilson Snyder

12:05 pm Veripool Veripool Software Update: The Veripool website software was upgraded today. This new version includes the ability to have private issues. If yo... Wilson Snyder

04:46 pm IPC::Locker IPC::Locker 1.489 Released: IPC::Locker 1.489 2012/01/12
**** Fix some false CPAN test failures.
Wilson Snyder
04:31 pm Verilog-mode Patch #429 (Closed): Remove interfaced ports from auto-inst of interfaces: I added 'verilog-auto-inst-interfaced-ports' with the opposite sense (to avoid the negation in the definition) to r77... Wilson Snyder
12:51 am Verilator Issue #431 (AskedReporter): typedef inside module causes internal error: Can you please attach a complete test and command line, preferably in test_regress format? The below works for me:
... Wilson Snyder
12:10 am Verilog-Perl Issue #428 (Rejected): Syntax error when "break" is used as block identifier for disable statement: break is a SystemVerilog keyword. Fix the code, or use the --language or related options to say you want only Verilo... Wilson Snyder

12:45 pm Verilog-mode Issue #430: Incorrect indentation in Verilog Mode v736: Here's another fragment that shows a similar issue, probably the same bug:... Alan Morgan

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