Activity

Wilson Snyder's activity

From 05/23/2012 to 06/21/2012

01:07 pm Verilog-Perl Issue #526 (Feature): Support UVM: The parser at present needs to know what is a class etc when tokens are recognized. However it's easily confused whe... Wilson Snyder

10:01 am Verilog-Perl Using: RE: Did anyone ever use the Parser as a stand-alone SV parser in a C++ project?: Predeclare, as in make the "class foo; endclass" you showed above.
Wilson Snyder

10:25 pm Verilog-Perl Using: RE: Did anyone ever use the Parser as a stand-alone SV parser in a C++ project?: As I said above, you need to predeclare the data type. Wilson Snyder
08:12 pm Verilog-Perl Using: RE: Did anyone ever use the Parser as a stand-alone SV parser in a C++ project?: That's where the bison grammar is generated, you're using it under the covers. Wilson Snyder

11:48 pm Verilog-Perl Using: RE: Did anyone ever use the Parser as a stand-alone SV parser in a C++ project?: Yes, why not just try it? The lexer is at least one symbol ahead of the parser, so it might not do what you want. Wilson Snyder
05:38 pm Verilog-Perl Using: RE: Did anyone ever use the Parser as a stand-alone SV parser in a C++ project?: Please file a "support UVM" or alternatively "don't require types predefined" bug and I'll follow up there. Wilson Snyder
05:32 pm Verilog-Perl Using: RE: Did anyone ever use the Parser as a stand-alone SV parser in a C++ project?: The parser requires all types to be predefined. This is required by the language standard. However I've debated fix... Wilson Snyder

01:48 am Verilog-mode Issue #525 (Closed): An Urgent question How to use AUTO_TEMPLATE to handle names of instanced mod...: See "vl-dir" in the AUTOINST help (Either under the Verilog menu, then Auto, then AUTOINST, or with M-x describe-func... Wilson Snyder

02:13 am Verilog-Perl Issue #524 (NoFixNeeded): Parser bug in processing compiler directives in comments: Wilson Snyder
01:12 am Verilog-Perl Issue #524 (AskedReporter): Parser bug in processing compiler directives in comments: It looks like your code is the one doing the searching for `ifndef, etc, as you're writing a raw parser that doesn't ... Wilson Snyder
12:35 am Verilator Development: RE: Behaviour when ignoring COMBDLY: What exactly does design compiler do with this in terms of the gates it generates? I'm skeptical there's an easy fix... Wilson Snyder
12:27 am Verilator Issue #523 (WillNotFix): search for package on import: IEEE strongly suggests it needs to be declared first, and the big three simulators agree it needs to be `included fir... Wilson Snyder

03:23 pm Verilog-mode Issue #522 (Closed): Expand $clog2 in AUTOINST param port widths: Thanks for the report and good test case. Fixed in r804.
Wilson Snyder
03:19 am Verilator Issue #521 (Closed): Problem with -DVL_LEAK_CHECKS: Fixed most leaks (rest should go away when other features go in).
When compiled with VL_LEAK_CHECKS, --debug-check... Wilson Snyder

07:24 pm Verilog-Perl Using: RE: Need a "simple" connectivity report: $module->is_libcell will be set if it's inside a `celldefine. Sorry it seems to be missing from the docs, I'll add it.
Wilson Snyder
02:59 am Verilator Issue #521: Problem with -DVL_LEAK_CHECKS: This is fixed in git, the core dump was due to recent changes for structs.
The check does report many leaks though... Wilson Snyder

08:18 pm Verilog-Perl Using: RE: Need a "simple" connectivity report: You can install it yourself, see [[Installing]].
Then download the kit and look at the Verilog::Getopt manpage and... Wilson Snyder

08:43 pm Verilog-mode Issue #520 (Feature): module back matching with regexp autos: \1 and \2 etc refer to the regexps in the pin name, and never have referred to the instance name. Some new syntax wo... Wilson Snyder

11:34 pm Verilog-Perl Using: RE: Need a "simple" connectivity report: Given the structural & no concats & presumably no cell arrays etc, yes it can do this. Someone probably has, but I d... Wilson Snyder
11:14 pm Verilog-Perl Using: RE: Did anyone ever use the Parser as a stand-alone SV parser in a C++ project?: I believe moving endParse as described will fix the problem of it being called before the endclass. If you have diff... Wilson Snyder

12:00 pm Verilog-Perl Using: RE: Did anyone ever use the Parser as a stand-alone SV parser in a C++ project?: Looks like endParse is sent when I set m_eof instead of when it is used. Try calling it instead on a <<EOF>> rule in... Wilson Snyder

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