Veripool

08/10/2012

11:57 pm Verilator Issue #544: Support associative arrays

Fixed lookup line to "mem_data[",y,"]".
Wilson Snyder

11:56 pm Verilator Issue #544: Support associative arrays

It's not too hard, just a lot of effort on details. First there's the parsing, and creating related Ast node types w... Wilson Snyder

11:42 pm Verilator Issue #546 (Assigned): Support static inside task

Actually by the standard "static" is the default unless the task is automatic, but verilator presently assumes everyt... Wilson Snyder

11:40 pm Verilator Issue #548 (Resolved): incorrect %Error: Duplicate declaration of CELLINLINE

Your test case was long because it was related to inlining, any large number of statements was needed to see it.
F... Wilson Snyder

08/09/2012

04:58 pm Verilog-mode Issue #547 (NoFixNeeded): Regex causes other escape characters to be invalid

Once regexps are used you need to backslash quote any backslashes. Use this... Wilson Snyder

02:11 am Verilator Issue #349 (Closed): logical shift of signed values

Fixed in 3.840 related to bug511.
Wilson Snyder

02:06 am Verilator Issue #227 (Closed): Bitwise reductions on signals with >1 packed dimension generates incorrect code

This was resolved back in 3.802. Wilson Snyder

02:00 am Verilator Issue #542 (Resolved): import package is broken under multiply instantiated cells

Fixed in git towards 3.841.
Wilson Snyder

01:58 am Verilator Issue #544 (Feature): Support associative arrays

Unfortunately not high priority for my usage, and requires moderate work as it's a dynamic construct. Perhaps you or ... Wilson Snyder

01:58 am Verilator Issue #545 (Feature): Support queues

Unfortunately not high priority for my usage, and requires moderate work as it's a dynamic construct. Perhaps you or ... Wilson Snyder

08/08/2012

01:49 am Verilator Issue #542: import package is broken under multiply instantiated cells

No, verilator has never implemented automatic package resolution, and it fails on both revisions the same.
Also ne... Wilson Snyder

12:36 am Verilator Issue #542 (AskedReporter): import package is broken under multiply instantiated cells

Sorry this works for me, please give a failing example in verilator test_regress format.
Wilson Snyder

08/07/2012

10:24 pm Verilator Issue #543 (Resolved): defparam inside generate does not work correctly

Fixed in git towards 3.841.
Wilson Snyder

11:12 am Verilator Usage: RE: Support for $finish_and_return

I don't want to do that because I want the tests to run under any simulator without VPI code etc being required. The... Wilson Snyder

11:08 am Verilator Usage: RE: "may be used uninitialized" depending on localparam expression

1 is NOT the same as 4'd1. 4'd1 is 4 bits wide, and parameters get the width of the object so the parameter is 4 bit... Wilson Snyder

11:05 am Verilator Usage: RE: Internal Error: Function not underneath a statement

Please file as a bug, thanks. Wilson Snyder

11:03 am Verilator Issue #543: defparam inside generate does not work correctly

Generates were first added in Verilog 2001, the same standard which made defparam a depreciated construct. Therefore... Wilson Snyder

08/06/2012

04:48 pm Verilator Installation: RE: Restrict verilator installation to a single directory

There's no way at present to have a single flat directory. Certainly you can live with some hierarchy (bin and inclu... Wilson Snyder

08/02/2012

03:53 pm Verilog-Perl Using: RE: 'always' block parser

I see, BTW I presume you mean the SigParser, not the Verilog::Parser.
Unfortunately you're right the SigParser doe... Wilson Snyder

02:07 pm Verilog-Perl Using: RE: 'always' block parser

The parser handles the full language (minus a few bugs). What exactly is your problem? Wilson Snyder

11:03 am Verilator Issue #541 (Resolved): Improper WIDTH warning on a parameterized module

Fixed in git towards 3.841.
Wilson Snyder

03:16 am Verilator Issue #541 (Assigned): Improper WIDTH warning on a parameterized module

I believe this was broken in the fix for bug470, the top-down order of parameter module processing was violated. I h... Wilson Snyder

07/31/2012

11:24 pm Verilator Issue #474 (Feature): Support inserting package symbols underneath module symbols

You are right, the bug fixed was part of your test case but not the main point, which remains unresolved.
Wilson Snyder

10:58 pm Verilator Issue #55 (Closed): Tristate: Tracing an inout signal is broken

In 3.840.
Wilson Snyder

10:58 pm Verilator Issue #499 (Closed): %Error: Internal Error: ...: ../V3Slice.cpp:418: Couldn't find a VarRef on t...

In 3.840.
Wilson Snyder

10:58 pm Verilator Issue #505 (Closed): %Error: ...: Expecting expression to be constant, but can't determine consta...

In 3.840.
Wilson Snyder

10:58 pm Verilator Issue #510 (Closed): Error with unsized elements in tristate select

In 3.840.
Wilson Snyder

10:57 pm Verilator Issue #474 (Closed): Support inserting package symbols underneath module symbols

In 3.840.
Wilson Snyder

10:57 pm Verilator Issue #51 (Closed): Mixing tristate and low-Z drivers. Error Msg unclear.

In 3.840.
Wilson Snyder

10:57 pm Verilator Issue #54 (Closed): Tristates break when a child modules does has no driver

In 3.840.
Wilson Snyder

10:56 pm Verilator Issue #534 (Closed): config_rev.pl not called when verilator used as a git submodule

In 3.840.
Wilson Snyder

10:56 pm Verilator Issue #530 (Closed): Compiler error with GCC 4.7.0

In 3.840.
Wilson Snyder

10:56 pm Verilator Issue #513 (Closed): Loop causes internal error

In 3.840.
Wilson Snyder

10:55 pm Verilator Issue #490 (Closed): %Error: Internal Error: ...: ../V3Link.cpp:113: Symbol table not found looki...

In 3.840.
Wilson Snyder

10:55 pm Verilator Issue #501 (Closed): Real data type lost/Expected real input to RTOIS

In 3.840.
Wilson Snyder

10:55 pm Verilator Issue #491 (Closed): %Error: ...: Expected integral (non-real) input to ITORD

In 3.840.
Wilson Snyder

10:55 pm Verilator Issue #511 (Closed): signed/unsigned mixed calculation with WIDTH warning off

In 3.840. Wilson Snyder

10:54 pm Verilator Issue #516 (Closed): suppress multiple warnings for the same issue

In 3.840. Wilson Snyder

10:54 pm Verilator Issue #413 (Closed): generate-conditional with short-circuited local expression

In 3.840. Wilson Snyder

10:54 pm Verilator Issue #478 (Closed): %Error: ...: Internal: Blocking <= assignment in non-clocked block, should h...

In 3.840. Wilson Snyder

10:54 pm Verilator Issue #488 (Closed): Support pmos, etc.

In 3.840. Wilson Snyder

10:54 pm Verilator Issue #462 (Closed): Support tri0/tri1

Wilson Snyder

10:53 pm Verilator Issue #462: Support tri0/tri1

In 3.840. Wilson Snyder

10:53 pm Verilator Issue #181 (Closed): Support struct and union

In 3.840.
Wilson Snyder

10:52 pm Verilator Verilator 3.840 Released

Verilator 3.840 2012/07/31 Beta
This version has large internal changes and may be less stable then the previous r... Wilson Snyder

07/29/2012

02:18 pm Verilator Issue #181 (Resolved): Support struct and union

Packed struct and unions are now in the git version towards 3.900. Note '{} is not supported yet, but will follow so... Wilson Snyder

07/28/2012

11:22 pm Verilog-Perl Issue #537: Explicit hierarchical reference not resolving in Verilog::Net (CELL outside of module...

Sorry was too brief.
After you add the new callback name to callbackgen, have VParseBison.y call it similar to the... Wilson Snyder

07/27/2012

10:51 pm Verilog-Perl Issue #518 (Closed): wrong return value check

In 3.316.
Wilson Snyder

10:51 pm Verilog-Perl Issue #507 (Closed): assign with value containing newline fails

In 3.316.
Wilson Snyder

10:50 pm Verilog-Perl Verilog-Perl 3.316 Released

Verilog::Language 3.316 2012/07/27
**** Fix newlines in radix values, bug507. [Walter Lavino]
**** Fix internal... Wilson Snyder

09:10 pm Verilog-mode Issue #539: AUTOs for wrapping a module around an interface

Do you think it should look for @(<signals>) in the clocking block and imply that they are inputs?
Wilson Snyder

07/26/2012

10:43 pm Verilog-Perl Issue #504 (NoFixNeeded): Vrename aborts when parsing a large netlist

Assuming resolved.
Wilson Snyder

10:41 pm Verilog-Perl Issue #537 (AskedReporter): Explicit hierarchical reference not resolving in Verilog::Net (CELL o...

Wilson Snyder

10:41 pm Verilog-Perl Issue #537: Explicit hierarchical reference not resolving in Verilog::Net (CELL outside of module...

Oh, no Verilog-Perl doesn't actually do anything with the bind. At the moment I unfortunately don't have the time to... Wilson Snyder

10:36 pm Verilator Issue #538 (Assigned): Mac OSX data types

There were some Mac issues fixed in the git version, though I'm not sure about that one. Please give it a try.
Wh... Wilson Snyder

07/25/2012

10:25 pm Verilog-Perl Using: RE: bind operator

Just fixed this in the git version, thanks for the good example. BTW if something breaks, please file a bug as somet... Wilson Snyder

07/24/2012

10:49 pm Verilator Issue #536 (Closed): Regression test driver does not generate initial VCD values

Thanks for the patch, committed. BTW to get the tests to pass needed to conditionality use !$self->sc_or_sp otherwis... Wilson Snyder

10:34 am Verilog-Perl Using: RE: Using VPreProc in C++

Perl tracks the definitions, not C++. If you need it all in C you'll need to replace many of the functions related t... Wilson Snyder

07/23/2012

02:05 pm Verilator Issue #535 (Assigned): SystemC 2.3.0 does not work with Verilator tests

Wilson Snyder

02:05 pm Verilator Issue #535: SystemC 2.3.0 does not work with Verilator tests

Yes, you need to
export SYSTEMC_CXX_FLAGS=-pthread
Annoyingly that wasn't needed in the pre-released 2.3.0.
... Wilson Snyder

07/22/2012

11:50 pm Verilator Issue #534 (Resolved): config_rev.pl not called when verilator used as a git submodule

Thanks for the report, simple enough to fix. Fixed in git towards 3.840++.
Wilson Snyder

07/20/2012

03:23 pm Verilator Issue #533 (Assigned): Missing width warning when part of a bus is compared

Actually there should be a WIDTH warning here to tell people what's odd.
Note also your test needs to compare only... Wilson Snyder

03:17 pm Verilator Issue #533: Missing width warning when part of a bus is compared

0 is 32 bits wide, not 6 bits. If you compare with 6'h0 you'll get what you expect.
Wilson Snyder

10:29 am Verilator Issue #533 (NoFixNeeded): Missing width warning when part of a bus is compared

Thanks for the good test, however I'm not sure why you think the answer should be 1, as VCS, NC and Verilator all agr... Wilson Snyder

07/19/2012

04:10 pm Verilator Issue #532 (Assigned): Support +systemverilogext+

Makes sense. FYI VCS supports
+systemverilogext+<ext>
+verilog1995ext+<ext>
+verilog2001ext+<ext>
So I'd sug... Wilson Snyder

07/17/2012

05:01 pm Verilator Issue #531: Combinatorial loop fails to converge

P.S. what they are probably really after is
always @(posedge clk or negedge clk)
y <= y + 1
Wilson Snyder

05:00 pm Verilator Issue #531 (AskedReporter): Combinatorial loop fails to converge

always @(non-edge) with only ='s indicates combinatorial logic. This I suspect won't synthesize, either, which is th... Wilson Snyder

07/15/2012

04:27 pm Verilator Issue #530 (Resolved): Compiler error with GCC 4.7.0

Thanks for the good patch set. Fixed in git towards 3.840+.
Wilson Snyder

03:44 pm Verilog-mode Patch #529 (Closed): Add batch mode for verilog-delete-trailing-whitespace

Fixed in rev809, thanks for the patch too.
Wilson Snyder

03:22 pm Verilog-Perl Issue #527 (AskedReporter): segmentation fault in Preproc.so

Sorry for the delay. Is the version of "flex" the same in both cases?
Based on the valgrind report, try this:
... Wilson Snyder

03:19 pm Verilator Issue #385: Dpi exported tasks with array inputs don't compile.

I'm not actively working on DPI improvements, so there will be a good wait. If you would like to try to make the imp... Wilson Snyder