0001-Support-interfaces-and-modports.patch - Verilator

b/src/Makefile_obj.in
188	188	V3Hashed.o \
189	189	V3Inline.o \
190	190	V3Inst.o \
	191	V3Interface.o \
191	192	V3Life.o \
192	193	V3LifePost.o \
193	194	V3Link.o \

     	BLOCKTEMP,
     	MODULETEMP,
     	STMTTEMP,
     	XTEMP
     	XTEMP,
             INTERFACE,      // Used to link Interfaces between modules
         };
         enum en m_e;
         inline AstVarType () {}
-...
     	    "?","GPARAM","LPARAM","GENVAR",
     	    "VAR","INPUT","OUTPUT","INOUT",
     	    "SUPPLY0","SUPPLY1","WIRE","IMPLICITWIRE","TRIWIRE","PORT",
     	    "BLOCKTEMP","MODULETEMP","STMTTEMP","XTEMP"};
     	    "BLOCKTEMP","MODULETEMP","STMTTEMP","XTEMP", "INTERFACE"};
     	return names[m_e]; }
       };
       inline bool operator== (AstVarType lhs, AstVarType rhs) { return (lhs.m_e == rhs.m_e); }

         this->AstNode::dump(str);
         if (littleEndian()) str<<" [LITTLE]";
+    }
     void AstInterfaceDType::dump(ostream& str) {
         this->AstNode::dump(str);
         if (interfacep()) { str<<" -> "; interfacep()->dump(str); }
         else { str<<" -> UNLINKED"; }
+    }
     void AstModportVar::dump(ostream& str) {
         this->AstNode::dump(str);
         str<<" "<<varType();
         if (varp()) { str<<" -> "; varp()->dump(str); }
         else { str<<" -> UNLINKED"; }
+    }
     void AstRefDType::dump(ostream& str) {
         this->AstNode::dump(str);
         if (defp()) { str<<" -> "; defp()->dump(str); }
-...
         if (varp()) { str<<" -> "; varp()->dump(str); }
         else { str<<" ->UNLINKED"; }
+    }
     void AstScopeAlias::dump(ostream& str) {
         this->AstNode::dump(str);
         if (aliasp()) { str<<" -> " << aliasp(); }
         else { str<<" ->UNLINKED"; }
+    }
     void AstVarRef::dump(ostream& str) {
         this->AstNode::dump(str);
         if (lvalue()) str<<" [LV] => ";

         void	implicit(bool flag) { m_implicit = flag; }
     };
     struct AstInterfaceDType : public AstNodeDType {
     private:
         AstInterface*	m_interfacep;
         string		m_name;
         string		m_varName;
         string		m_modportName;
         AstModport*		m_modportp;
     public:
         AstInterfaceDType(FileLine* fl, const string& name)
     	: AstNodeDType(fl), m_interfacep(NULL), m_name(name), m_varName(name),
     	  m_modportName(""), m_modportp(NULL) { }
         AstInterfaceDType(FileLine* fl, const string& name, const string& modport)
     	: AstNodeDType(fl), m_interfacep(NULL), m_name(name), m_varName(name),
     	  m_modportName(modport), m_modportp(NULL) { }
         ASTNODE_NODE_FUNCS(InterfaceDType, INTERFACEDTYPE)
         // METHODS
         virtual void dump(ostream& str=cout);
         virtual string name() const { return m_name; }
         virtual AstBasicDType* basicp() const { return NULL; }
         virtual int widthAlignBytes() const { return 1; }
         virtual int widthTotalBytes() const { return 1; }
         virtual AstNodeDType* skipRefp() const { return (AstNodeDType*)this; }
         AstInterface* interfacep() const { return m_interfacep; }
         void interfacep(AstInterface* nodep) { m_interfacep=nodep; }
         string varName() const { return m_varName; }
         void varName(const string& name) { m_varName=name; }
         string modportName() const { return m_modportName; }
         void modportName(const string& name) { m_modportName=name; }
         AstModport* modportp() const { return m_modportp; }
         void modportp(AstModport* modportp) { m_modportp=modportp; }
         bool isModport() { return !!modportName().size(); }
     };
     struct AstRefDType : public AstNodeDType {
     private:
         AstTypedef*	m_defp;
-...
         // A variable (in/out/wire/reg/param) inside a module
     private:
         string	m_name;		// Name of variable
         string	m_origName;	// Original name before dot addition
         AstVarType	m_varType;	// Type of variable
         bool	m_input:1;	// Input or inout
         bool	m_output:1;	// Output or inout
-...
     public:
         AstVar(FileLine* fl, AstVarType type, const string& name, AstNodeDType* dtypep)
     	:AstNode(fl)
     	, m_name(name) {
     	, m_name(name), m_origName(name) {
     	init();
     	combineType(type); setOp1p(dtypep);
     	if (dtypep && dtypep->basicp()) {
-...
+        }
         AstVar(FileLine* fl, AstVarType type, const string& name, AstLogicPacked, int wantwidth)
     	:AstNode(fl)
     	, m_name(name) {
     	, m_name(name), m_origName(name) {
     	init();
     	combineType(type);
     	setOp1p(new AstBasicDType(fl, AstLogicPacked(), wantwidth));
-...
+        }
         AstVar(FileLine* fl, AstVarType type, const string& name, AstVar* examplep)
     	:AstNode(fl)
     	, m_name(name) {
     	, m_name(name), m_origName(name) {
     	init();
     	combineType(type);
     	if (examplep->dtypep()) {
-...
         ASTNODE_NODE_FUNCS(Var, VAR)
         virtual void dump(ostream& str);
         virtual string name()	const { return m_name; }		// * = Var name
         string origName()		const { return m_origName; }		// * = Original name
         virtual bool maybePointedTo() const { return true; }
         virtual bool broken() const { return !dtypep(); }
         AstVarType	varType()	const { return m_varType; }		// * = Type of variable
         AstVarType	varType(AstVarType::en type) { m_varType == type; }
         void varType2Out() { m_tristate=0; m_input=0; m_output=1; }
         void varType2In() {  m_tristate=0; m_input=1; m_output=0; }
         string	scType() const;	  // Return SysC type: bool, uint32_t, uint64_t, sc_bv
-...
         bool	isPrimaryIO() const { return m_primaryIO; }
         bool	isPrimaryIn() const { return isPrimaryIO() && isInput(); }
         bool	isIO() const  { return (m_input||m_output); }
         bool	isInterface() const { return (varType()==AstVarType::INTERFACE); }
         bool	isSignal() const  { return (varType()==AstVarType::WIRE || varType()==AstVarType::IMPLICITWIRE
     					    || varType()==AstVarType::VAR); }
         bool	isTemp() const { return (varType()==AstVarType::BLOCKTEMP || varType()==AstVarType::MODULETEMP
-...
         void	circular(bool flag) { m_circular = flag; }
     };
     struct AstScopeAlias : public AstVarScope {
         // An Alias to another Scope
     private:
         AstScope*	m_aliasp;	// The scope this points to
     public:
         AstScopeAlias(FileLine* fl, AstScope* scopep, AstVar* varp, AstScope* aliasp)
     	:AstVarScope(fl, scopep, varp), m_aliasp(aliasp) {}
         ASTNODE_NODE_FUNCS(ScopeAlias, SCOPEALIAS)
         AstScope* aliasp() const { return m_aliasp; }
         void aliasp(AstScope* aliasp) { m_aliasp = aliasp; }
         virtual void dump(ostream& str);
         virtual string name() const {return scopep()->name()+"."+varp()->name();}	// * = Var name
     };
     struct AstVarRef : public AstNodeVarRef {
         // A reference to a variable (lvalue or rvalue)
         AstVarRef(FileLine* fl, const string& name, bool lvalue)
-...
         void packagep(AstPackage* nodep) { m_packagep=nodep; }
     };
     struct AstInterface : public AstNodeModule {
         // A module declaration
         AstInterface(FileLine* fl, const string& name)
     	: AstNodeModule (fl,name) { }
         ASTNODE_NODE_FUNCS(Interface, INTERFACE)
     };
     struct AstModportVar : public AstNode {
         // A Var under a modport
     private:
         string	m_name;		// Name of the variable
         AstVarType	m_type;		// Type of the variable
         AstVar*	m_varp;		// Link to the actual Var
     public:
         AstModportVar(FileLine* fl, const string& name, AstVarType::en type)
     	: AstNode(fl), m_name(name), m_type(type), m_varp(NULL) { }
         ASTNODE_NODE_FUNCS(ModportVar, MODPORTVAR)
         virtual void dump(ostream& str);
         AstVarType	varType()	const { return m_type; }		// * = Type of variable
         virtual string name()	const { return m_name; }
         bool	isInput() const { return (varType()==AstVarType::INPUT || varType()==AstVarType::INOUT); }
         bool	isOutput() const { return (varType()==AstVarType::OUTPUT || varType()==AstVarType::INOUT); }
         AstVar*	varp()	const { return m_varp; }		// [After Link] Pointer to variable
         void	varp(AstVar* varp) { m_varp=varp; }
     };
     struct AstModport : public AstNode {
         // A modport in an interface
     private:
         string	m_name;		// Name of the modport
     public:
         AstModport(FileLine* fl, const string& name, AstModportVar* varsp)
     	: AstNode(fl), m_name(name) {
             addNOp1p(varsp); }
         virtual string name()	const { return m_name; }
         ASTNODE_NODE_FUNCS(Modport, MODPORT)
         AstModportVar* varsp()	const { return op1p()->castModportVar(); }	// op1 = List of Vars
     };
     struct AstCell : public AstNode {
         // A instantiation cell or interface call (don't know which until link)
     private:
-...
         string	m_origName;	// Original name before dot addition
         string	m_modName;	// Module the cell instances
         AstNodeModule*	m_modp;		// [AfterLink] Pointer to module instanced
         bool	m_hasVar;	// True if a Var has been created for this cell
     public:
         AstCell(FileLine* fl, const string& instName, const string& modName,
     	    AstPin* pinsp, AstPin* paramsp, AstRange* rangep)
     	: AstNode(fl)
     	, m_name(instName), m_origName(instName), m_modName(modName)
     	, m_modp(NULL) {
     	, m_modp(NULL), m_hasVar(false) {
     	addNOp1p(pinsp); addNOp2p(paramsp); setNOp3p(rangep); }
         ASTNODE_NODE_FUNCS(Cell, CELL)
         // No cloneRelink, we presume cloneee's want the same module linkages
-...
         void addPinsp(AstPin* nodep) { addOp1p(nodep); }
         void addParamsp(AstPin* nodep) { addOp2p(nodep); }
         void modp(AstNodeModule* nodep)	{ m_modp = nodep; }
         virtual bool hasVar()	const { return m_hasVar; }
         virtual void hasVar(bool status) { m_hasVar = status; }
     };
     struct AstCellInline : public AstNode {
-...
+        }
     };
     struct AstAssignVarScope : public AstNodeAssign {
         // Assign two VarScopes to each other
         AstAssignVarScope(FileLine* fileline, AstNode* lhsp, AstNode* rhsp)
     	: AstNodeAssign(fileline, lhsp, rhsp) { }
         ASTNODE_NODE_FUNCS(AssignVarScope, ASSIGNVARSCOPE)
         virtual AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) { return new AstAssignVarScope(this->fileline(), lhsp, rhsp); }
     };
     struct AstPull : public AstNode {
     private:
         bool m_direction;

         virtual void visit(AstAssignAlias* nodep, AstNUser*) {
     	// Don't perform any optimizations, keep the alias around
+        }
         virtual void visit(AstAssignVarScope* nodep, AstNUser*) {
     	// Don't perform any optimizations, the node won't be linked yet
+        }
         virtual void visit(AstAssignW* nodep, AstNUser*) {
     	nodep->iterateChildren(*this);
     	if (replaceNodeAssign(nodep)) return;

     		    m_modp->addStmtp(new AstAssignW(nodep->fileline(),
     						    new AstVarRef(nodep->fileline(), nodep, true),
     						    exprconstp->cloneTree(true)));
     		} else {
     		} else if (!nodep->isInterface()) {
     		    m_modp->addStmtp(new AstAssignAlias(nodep->fileline(),
     							new AstVarRef(nodep->fileline(), nodep, true),
     							new AstVarRef(nodep->fileline(), exprvarrefp->varp(), false)));
     		    AstNode* nodebp=exprvarrefp->varp();
     		    nodep ->fileline()->modifyStateInherit(nodebp->fileline());
     		    nodebp->fileline()->modifyStateInherit(nodep ->fileline());
     		} else {
     		    m_modp->addStmtp(new AstAssignVarScope(nodep->fileline(),
     							new AstVarRef(nodep->fileline(), nodep, true),
     							new AstVarRef(nodep->fileline(), exprvarrefp->varp(), false)));
     		    AstNode* nodebp=exprvarrefp->varp();
     		    nodep ->fileline()->modifyStateInherit(nodebp->fileline());
     		    nodebp->fileline()->modifyStateInherit(nodep ->fileline());
+    		}
+    	    }
     	    // Variable under the inline cell, need to rename to avoid conflicts
-...
         virtual void visit(AstNodeModule* nodep, AstNUser*) {
     	m_stmtCnt = 0;
     	m_modp = nodep;
     	m_modp->user2(true);  // Allowed = true
     	if (nodep->castInterface()) {
     	    m_modp->user2(false);
     	} else {
     	    m_modp->user2(true);  // Allowed = true
+    	}
     	if (m_modp->modPublic()) cantInline("modPublic");
     	//
     	nodep->iterateChildren(*this);
-...
     	nodep->iterateChildren(*this);
     	m_stmtCnt = oldcnt;
+        }
         virtual void visit(AstInterfaceDType* nodep, AstNUser*) {
     	// Unsupported: Inlining of modules with interfaces
     	m_modp->user2(false);
+        }
         //--------------------
         // Default: Just iterate
         virtual void visit(AstNode* nodep, AstNUser*) {

     		     exprp);
     		m_modp->addStmtp(assp);
     		if (debug()>=9) assp->dumpTree(cout,"     _new: ");
     	    } else if (nodep->modVarp()->isInterface()) {
     		// Create an AstAssignVarScope for Vars to Cells so we can link with their scope later
     		AstNode* rhsp = new AstVarXRef (exprp->fileline(), nodep->modVarp()->name(), m_cellp->name(), false);
     		rhsp->widthSignedFrom(nodep);
     		if (AstVarRef* refp = exprp->castVarRef()) {
     		    refp->varp(NULL);
     		} else {
     		    exprp->v3fatalSrc("Interfaces: Pin is not connected to a VarRef");
+    		}
     		AstAssignVarScope* assp = new AstAssignVarScope(exprp->fileline(), exprp, rhsp);
     		m_modp->addStmtp(assp);
     	    } else {
     		nodep->v3error("Assigned pin is neither input nor output");
+    	    }

     //*************************************************************************
     // DESCRIPTION: Verilator: Parse module/signal name references
     //
     // Code available from: http://www.veripool.org/verilator
     //
     // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
     //
     //*************************************************************************
     //
     // Copyright 2003-2010 by Wilson Snyder.  This program is free software; you can
     // redistribute it and/or modify it under the terms of either the GNU
     // Lesser General Public License Version 3 or the Perl Artistic License
     // Version 2.0.
     //
     // Verilator is distributed in the hope that it will be useful,
     // but WITHOUT ANY WARRANTY; without even the implied warranty of
     // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     // GNU General Public License for more details.
     //
     //*************************************************************************
     // Interface TRANSFORMATIONS:
     //	Top-down traversal:
     //	  MODPORT
     //	    Delete tree
     //*************************************************************************
     #include "config_build.h"
     #include "verilatedos.h"
     #include <cstdio>
     #include <cstdarg>
     #include <unistd.h>
     #include "V3Global.h"
     #include "V3Interface.h"
     #include "V3Ast.h"
     //######################################################################
     // Lint interfaces/modports, as a visitor of each AstNode
     class InterfaceCleanup : public AstNVisitor {
     private:
         // NODE STATE
         // ENUMS
         // STATE
         // METHODS
         virtual void visit(AstModport* nodep, AstNUser*) {
     	// Modports aren't needed anymore, delete them
     	nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
+        }
         virtual void visit(AstNode* nodep, AstNUser*) {
     	// Default: Just iterate
     	nodep->iterateChildren(*this);
+        }
     public:
         // CONSTUCTORS
         InterfaceCleanup(AstNetlist* rootp) {
     	rootp->accept(*this);
+        }
         virtual ~InterfaceCleanup() {}
     };
     //######################################################################
     // Interface class functions
     void V3Interface::lint(AstNetlist* rootp) {
         UINFO(4,__FUNCTION__<<": "<<endl);
         InterfaceCleanup visitor(rootp);
+    }

     // -*- C++ -*-
     //*************************************************************************
     // DESCRIPTION: Verilator: Link modules/signals together
     //
     // Code available from: http://www.veripool.org/verilator
     //
     // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
     //
     //*************************************************************************
     //
     // Copyright 2003-2009 by Wilson Snyder.  This program is free software; you can
     // redistribute it and/or modify it under the terms of either the GNU
     // Lesser General Public License Version 3 or the Perl Artistic License
     // Version 2.0.
     //
     // Verilator is distributed in the hope that it will be useful,
     // but WITHOUT ANY WARRANTY; without even the implied warranty of
     // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     // GNU General Public License for more details.
     //
     //*************************************************************************
     #ifndef _V3INTERFACE_H_
     #define _V3INTERFACE_H 1
     #include "config_build.h"
     #include "verilatedos.h"
     #include "V3Error.h"
     #include "V3Ast.h"
     //============================================================================
     class V3Interface {
     public:
         static void lint(AstNetlist* nodep);
     };
     #endif // Guard

     	nodep->iterateChildren(*this);
+        }
         virtual void visit(AstCell* nodep, AstNUser*) {
     	// Cell: Resolve its filename.  If necessary, parse it.
     	m_cellp = nodep;
     	if (m_idState==ID_FIND) {
     	    // Add to list of all cells, for error checking and defparam's
     	    findAndInsertAndCheck(nodep, nodep->name());
+    	}
     	if (!nodep->modp()) {
     	    nodep->v3fatalSrc("Cell has unlinked module"); // V3LinkCell should have errored out
+    	}
     	else {
     	    // Need to pass the module info to this cell, so we can link up the pin names
     	    if (m_idState==ID_RESOLVE) {
     	    if (m_idState==ID_FIND) {
     		if (AstInterface* interfacep = nodep->modp()->castInterface()) {
     		    if (!nodep->hasVar()) {
     			// If the Cell connects to an interface, create a new Var with a CellDType
     			AstNodeDType* iDTypep = new AstInterfaceDType(nodep->fileline(), interfacep->name());
     			iDTypep->castInterfaceDType()->interfacep(nodep->modp()->castInterface());
     			AstVar* varp = new AstVar(nodep->fileline(), AstVarType::INTERFACE, nodep->name(), iDTypep);
     			nodep->addNext(varp);
+    		    }
     		} else {
     		    // Add to list of all cells, for error checking and defparam's
     		    findAndInsertAndCheck(nodep, nodep->name());
+    		}
     	    } else if (m_idState==ID_RESOLVE) {
     		// Need to pass the module info to this cell, so we can link up the pin names
     		m_cellVarsp = nodep->modp()->user4p()->castSymTable();
     		UINFO(4,"(Backto) Link Cell: "<<nodep<<endl);
     		//if (debug()) { nodep->dumpTree(cout,"linkcell:"); }
-...
     	// This is done bottom up in the LinkBotupVisitor stage
+        }
         virtual void visit(AstInterfaceDType* nodep, AstNUser*) {
     	nodep->iterateChildren(*this);
     	// Link Modport names to the Modport Node under the Interface
     	if (m_idState==ID_RESOLVE) {
     	    if (nodep->isModport() && !nodep->modportp()) {
     		for (AstNode* subnodep=nodep->interfacep()->stmtsp(); subnodep; subnodep = subnodep->nextp()) {
     		    if (AstModport* modportp = subnodep->castModport()) {
     			if (modportp->name() == nodep->modportName()) {
     			    nodep->modportp(modportp);
     			    UINFO(4,"Link Modport: "<<modportp<<endl);
+    			}
+    		    }
+    		}
+    	    }
+    	}
+        }
         virtual void visit(AstModport* nodep, AstNUser*) {
     	nodep->iterateChildren(*this);
+        }
         virtual void visit(AstModportVar* nodep, AstNUser*) {
     	nodep->iterateChildren(*this);
     	if (m_idState==ID_RESOLVE) {
     	    AstVar* varp = m_curVarsp->findIdUpward(nodep->name())->castVar();
     	    nodep->varp(varp);
     	    UINFO(4,"Link ModportVar: "<<nodep<<endl);
+    	}
+        }
         virtual void visit(AstPort* nodep, AstNUser*) {
     	// Port: Stash the pin number
     	if (!m_curVarsp) nodep->v3fatalSrc("Port not under module??\n");
-...
     	    AstVar* refp = m_curVarsp->findIdFlat(nodep->name())->castVar();
     	    if (!refp) {
     		nodep->v3error("Input/output/inout declaration not found for port: "<<nodep->prettyName());
     	    } else if (!refp->isIO()) {
     		nodep->v3error("Pin is not an in/out/inout: "<<nodep->prettyName());
     	    } else if (!refp->isIO() && !refp->isInterface()) {
     		nodep->v3error("Pin is not an in/out/inout/interface: "<<nodep->prettyName());
     	    } else {
     		symsInsert("__pinNumber"+cvtToStr(nodep->pinNum()), refp);
     		refp->user2(true);
-...
     		    return;
+    		}
     		nodep->v3error("Pin not found: "<<nodep->prettyName());
     	    } else if (!refp->isIO() && !refp->isParam()) {
     		nodep->v3error("Pin is not an in/out/inout/param: "<<nodep->prettyName());
     	    } else if (!refp->isIO() && !refp->isParam() && !refp->isInterface()) {
     		nodep->v3error("Pin is not an in/out/inout/param/interface: "<<nodep->prettyName());
     	    } else {
     		nodep->modVarp(refp);
+    	    }

     	//if (debug()>=9) m_mods.dump(cout, "-syms: ");
+        }
         virtual void visit(AstInterfaceDType* nodep, AstNUser*) {
     	// Cell: Resolve its filename.  If necessary, parse it.
     	if (!nodep->interfacep()) {
     	    UINFO(4,"Link Cell: "<<nodep<<endl);
     	    // Use findIdUpward instead of findIdFlat; it doesn't matter for now
     	    // but we might support modules-under-modules someday.
     	    AstNodeModule* modp = m_mods.findIdUpward(nodep->name())->castNodeModule();
     	    if (!modp) {
     		// Read-subfile
     		V3Parse parser (v3Global.rootp(), m_filterp);
     		parser.parseFile(nodep->fileline(), nodep->name(), false);
     		V3Error::abortIfErrors();
     		// We've read new modules, grab new pointers to their names
     		readModNames();
     		// Check again
     		modp = m_mods.findIdUpward(nodep->name())->castNodeModule();
     		if (!modp) {
     		    nodep->v3error("Can't resolve interface reference: "<<nodep->name());
+    		}
+    	    }
     	    if (modp) {
     		// Track module depths, so can sort list from parent down to children
     		new V3GraphEdge(&m_graph, vertex(m_modp), vertex(modp), 1, false);
     		nodep->interfacep(modp->castInterface());
+    	    }
+    	}
+        }
     public:
         // CONSTUCTORS
         LinkCellsVisitor(AstNetlist* rootp, V3InFilter* filterp) {

         virtual string modName() const { return (modp() ? modp()->origName() : "*NULL*"); }
         virtual string cellName() const { return (cellp() ? cellp()->origName() : "*NULL*"); }
         virtual string name() const { return (string)("C:")+cellName()+" M:"+modName(); }
         virtual string dotColor() const { return (modp()->castInterface() ? "green" : "black"); }
     };
     class LinkDotInlineVertex : public LinkDotBaseVertex {
-...
         // TYPES
         typedef std::multimap<string,LinkDotCellVertex*> NameScopeMap;
         typedef std::multimap<string,AstScope*> NameAstScopeMap;
         typedef std::map<string,string> ScopenameAliasMap;
         // MEMBERS
         LinkDotGraph	m_graph;		// Graph of hierarchy
         NameScopeMap	m_nameScopeMap;		// Hash of scope referenced by non-pretty textual name
         NameAstScopeMap	m_nameAstScopeMap;	// Hash of AstScope nodes referenced by non-pretty textual name
         ScopenameAliasMap	m_scopenameMap;		// Map of scopename aliases
         bool		m_forPrearray;		// Compress cell__[array] refs
         bool		m_forScopeCreation;	// Remove VarXRefs for V3Scope
     public:
-...
+    	}
     	return iter->second;
+        }
         void insertScopeAlias(const string& lhs, const string& rhs) {
     	m_scopenameMap.insert(make_pair(lhs, rhs));
+        }
         void insertScope(AstScope* nodep) {
     	m_nameAstScopeMap.insert(make_pair(nodep->name(), nodep));
+        }
         AstScope* findScopeByName(const string& scopename, bool useAlias) {
     	NameAstScopeMap::iterator iter = m_nameAstScopeMap.find(scopename);
     	if (iter == m_nameAstScopeMap.end()) {
     	    if (useAlias) {
     		ScopenameAliasMap::iterator itera = m_scopenameMap.find(scopename);
     		if (itera != m_scopenameMap.end())
     		    return findScopeByName(itera->second, useAlias);
+    	    }
     	    return NULL;
+    	}
     	return iter->second;
+        }
         void dump() {
     	if (debug()>=6) m_graph.dumpDotFilePrefixed("linkdot");
+        }
-...
     class LinkDotFindVisitor : public AstNVisitor {
     private:
         // TYPEs
         typedef std::multimap<AstInterfaceDType*,LinkDotCellVertex*> InterfaceVarMap;
         // STATE
         LinkDotState*	m_statep;	// State to pass between visitors, including symbol table
         LinkDotCellVertex*	m_cellVxp;	// Vertex for current module
         LinkDotBaseVertex*	m_inlineVxp;	// Vertex for current module, possibly a fake inlined one
         string		m_scope;	// Scope text
         AstBegin*		m_beginp;	// Current Begin/end block
         AstInterfaceDType*	m_interfaceDTypep;	// InterfaceDType for the current Var
         InterfaceVarMap	m_interfaceVarMap;	// A map of unconnected Interface Vars
         int debug() { return LinkDotState::debug(); }
-...
+        }
         virtual void visit(AstScope* nodep, AstNUser*) {
     	if (!m_statep->forScopeCreation()) v3fatalSrc("Scopes should only exist right after V3Scope");
     	// Ignored.  Processed in next step
     	// Store the scope in case it is aliased elsewhere (Interfaces). Otherwise ignored.  Processed in next step
     	m_statep->insertScope(nodep);
+        }
         virtual void visit(AstCell* nodep, AstNUser*) {
     	UINFO(5,"   CELL under "<<m_scope<<" is "<<nodep<<endl);
-...
     	m_cellVxp = oldVxp;
     	m_inlineVxp = oldInlineVxp;
+        }
         virtual void visit(AstInterfaceDType* nodep, AstNUser*) {
     	m_interfaceDTypep = nodep;
     	nodep->iterateChildren(*this);
+        }
         virtual void visit(AstCellInline* nodep, AstNUser*) {
     	UINFO(5,"   CELLINLINE under "<<m_scope<<" is "<<nodep<<endl);
     	LinkDotBaseVertex* aboveVxp = m_inlineVxp;
-...
     	m_beginp = oldbegin;
+        }
         virtual void visit(AstVar* nodep, AstNUser*) {
     	if (!m_statep->forScopeCreation()
     	    && !m_beginp	// For now, we don't support xrefs into begin blocks
     	    && !nodep->isFuncLocal()) {
     	// Look for any InterfaceDTypes, these use dotted variables
     	m_interfaceDTypep = NULL;
     	nodep->iterateChildren(*this);
     	if (m_interfaceDTypep && !m_statep->forScopeCreation()) {
     	    // Interfaces need to be added as sub-cells and syms, but not before we've found all the modules
     	    m_interfaceDTypep->varName(nodep->origName());
     	    m_interfaceVarMap.insert(make_pair(m_interfaceDTypep, m_cellVxp));
     	    m_statep->insertSym(m_cellVxp, nodep->name(), nodep);
     	} else {
     	    UINFO(9,"       Not allowing dot refs to: "<<nodep<<endl);
     	    if (!m_statep->forScopeCreation()
     		&& !m_beginp	// For now, we don't support xrefs into begin blocks
     		&& !nodep->isFuncLocal()) {
     		m_statep->insertSym(m_cellVxp, nodep->name(), nodep);
     	    } else {
     		UINFO(9,"       Not allowing dot refs to: "<<nodep<<endl);
+    	    }
+    	}
+        }
         virtual void visit(AstNodeFTask* nodep, AstNUser*) {
-...
     	m_cellVxp = NULL;
     	m_statep = statep;
     	m_beginp = NULL;
     	m_interfaceDTypep = NULL;
     	//
     	rootp->accept(*this);
     	// Insert any interfaces as sub-cells
     	InterfaceVarMap::iterator iter = m_interfaceVarMap.begin();
     	for (; iter != m_interfaceVarMap.end(); ++iter) {
     	    AstInterfaceDType* interfaceDTypep = iter->first;
     	    LinkDotCellVertex* aboveVxp = iter->second;
     	    LinkDotCellVertex* cellVxp = m_statep->findModScope(interfaceDTypep->interfacep());
     	    aboveVxp->insertSubcellName(interfaceDTypep->varName(), cellVxp);
+    	}
+        }
         virtual ~LinkDotFindVisitor() {}
     };
-...
     class LinkDotScopeVisitor : public AstNVisitor {
     private:
         // TYPEs
         typedef std::map<string,LinkDotCellVertex*> NameScopeVxpMap;
         // STATE
         AstScope*		m_scopep;	// The current scope
         LinkDotState*	m_statep;	// State to pass between visitors, including symbol table
         LinkDotCellVertex*	m_cellVxp;	// Vertex for current module
         NameScopeVxpMap	m_scopeMap;	// Map of unlinked scope alias to CellVertex
         int debug() { return LinkDotState::debug(); }
-...
     	// Using the CELL names, we created all hierarchy.  We now need to match this Scope
     	// up with the hierarchy created by the CELL names.
     	m_cellVxp = m_statep->findScope(nodep);
     	m_scopep = nodep;
     	nodep->iterateChildren(*this);
     	m_cellVxp = NULL;
+        }
-...
     	    m_statep->insertSym(m_cellVxp, nodep->varp()->name(), nodep);
+    	}
+        }
         virtual void visit(AstScopeAlias* nodep, AstNUser*) {
     	// Link the ScopeAlias to its Scope, may be NULL
     	AstScope* scope = m_statep->findScopeByName(nodep->name(), false);
     	if (scope) {
     	    nodep->aliasp(scope);
     	} else {
     	    NameScopeVxpMap::const_iterator iter = m_scopeMap.find(nodep->name());
     	    if (iter == m_scopeMap.end()) {
     		nodep->v3fatalSrc("Could not link scope for "+nodep->varp()->name());
     	    } else {
     		m_cellVxp->insertSubcellName(nodep->varp()->name(), iter->second);
+    	    }
+    	}
+        }
         virtual void visit(AstNodeFTask* nodep, AstNUser*) {
     	m_statep->insertSym(m_cellVxp, nodep->name(), nodep);
     	// No recursion, we don't want to pick up variables
+        }
         virtual void visit(AstAssignVarScope* nodep, AstNUser*) {
     	LinkDotCellVertex* linkedVxp = NULL;
     	string lhspScopename;
     	string rhspScopename;
     	if (AstVarRef* refp = nodep->lhsp()->castVarRef()) {
     	    lhspScopename = m_scopep->name()+"."+refp->name();
     	    AstScope* scopep = m_statep->findScopeByName(lhspScopename, true);
     	    LinkDotCellVertex* scopeVxp = m_statep->findScope(scopep);
     	    if (scopep) {
     		UINFO(5, "       Found a linked scope: "<<lhspScopename<<endl);
     		linkedVxp = scopeVxp;
     	    } else {
     		nodep->v3fatalSrc("Unsupported: Found a scopep on a VarXRef");
+    	    }
     	} else {
     	    nodep->v3fatalSrc("Unsupported: Non VarRef on lhsp of AssignVarScope");
+    	}
     	if (AstVarXRef* refp = nodep->rhsp()->castVarXRef()) {
     	    rhspScopename = m_scopep->name()+"."+refp->dotted()+"."+refp->name();
     	    AstScope* scopep = m_statep->findScopeByName(rhspScopename, true);
     	    if (scopep) {
     		UINFO(5,"       "<<scopep<<endl);
     		nodep->v3fatalSrc("Unsupported: Found a scopep on a VarXRef");
     	    } else {
     		UINFO(5, "       Found an unlinked scope: "<<rhspScopename<<endl);
     		m_scopeMap.insert(make_pair(rhspScopename,linkedVxp));
     		m_statep->insertScopeAlias(rhspScopename, lhspScopename);
+    	    }
     	} else {
     	    nodep->v3fatalSrc("Unsupported: Non VarXRef on rhsp of AssignVarScope");
+    	}
     	// We have stored the link, we don't need these any more
     	nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
+        }
         virtual void visit(AstAssignAlias* nodep, AstNUser*) {
     	// Track aliases created by V3Inline; if we get a VARXREF(aliased_from)
     	// we'll need to replace it with a VARXREF(aliased_to)
-...
     		nodep->varp(varp);
     		UINFO(7,"         Resolved "<<nodep<<endl);  // Also prints varp
     		if (!nodep->varp()) {
     		    // If this is an interface, that might be a modport not a signal
     		    LinkDotCellVertex* cellVxp = dynamic_cast<LinkDotCellVertex*>(dotVxp);
     		    if (cellVxp) {
     			AstInterface* interfacep = cellVxp->modp()->castInterface();
     			if (interfacep) {
     			    // Look for a modport under the Interface
     			    for (AstNode* subnodep=interfacep->stmtsp(); subnodep; subnodep = subnodep->nextp()) {
     			        if (AstModport* modportp = subnodep->castModport()) {
     				    if (modportp->name() == nodep->name()) {
     					// Change this VarXRef into a VarRef and link it to the Var
     					AstVar* varp = (m_statep->findSym(m_cellVxp, nodep->dotted(), baddot)
     							->castVar());  // maybe NULL
     					if (!varp) {
     					    nodep->v3error("Can't find definition of '"<<baddot<<"' (interface) in dotted signal: "<<nodep->dotted()+"."+nodep->prettyName());
     					    return;
+    					}
     					AstVarRef* refp = new AstVarRef(nodep->fileline(), varp, false);
     					nodep->replaceWith(refp);
     					// :TODO: byronb - Link the modport to the InterfaceDType under the Var
     					return;
+    				    }
+    				}
+    			    }
+    			}
+    		    }
     		    nodep->v3error("Can't find definition of '"<<baddot<<"' in dotted signal: "<<nodep->dotted()+"."+nodep->prettyName());
     		    okVxp->errorScopes(nodep);
+    		}

     		pinp->modVarp(oldvarp);
     		pinp->widthSignedFrom(oldvarp);
     		cellp->addPinsp(pinp);
     	    } else if (oldvarp->isInterface()) {
     		// Link the interface at the top-level
     		AstInterfaceDType* dtypep = oldvarp->dtypep()->castInterfaceDType();
     		if (!dtypep || !dtypep->isModport())
     		    continue;
     		for (AstNode* inodep=dtypep->modportp()->varsp(); inodep; inodep = inodep->nextp()) {
     		    AstModportVar* ivarp = inodep->castModportVar();
     		    if (ivarp) {
     			AstVar* newvarp = ivarp->varp()->cloneTree(false);
     			newvarp->name(oldvarp->name()+"__DOT__"+newvarp->name());
     			newvarp->varType(ivarp->varType());
     			if (ivarp->isInput()) {
     			    newvarp->varType2In();
     			    AstVarXRef* lhsp = new AstVarXRef(newvarp->fileline(), ivarp->varp()->name(),
     							      oldvarp->name(), true);
     			    AstVarRef* rhsp = new AstVarRef(newvarp->fileline(), newvarp->name(), false);
     			    rhsp->varp(newvarp);
     			    AstAssignW* assignp = new AstAssignW(newvarp->fileline(), lhsp, rhsp);
     			    lhsp->widthSignedFrom(newvarp);
     			    rhsp->widthSignedFrom(newvarp);
     			    assignp->widthSignedFrom(newvarp);
     			    oldmodp->addStmtp(newvarp);
     			    oldmodp->addStmtp(assignp);
     			} else {
     			    newvarp->varType2Out();
     			    AstVarRef* lhsp = new AstVarRef(newvarp->fileline(), newvarp->name(), true);
     			    AstVarXRef* rhsp = new AstVarXRef(newvarp->fileline(), ivarp->varp()->name(),
     							      oldvarp->name(), false);
     			    lhsp->varp(newvarp);
     			    AstAssignW* assignp = new AstAssignW(newvarp->fileline(), lhsp, rhsp);
     			    lhsp->widthSignedFrom(newvarp);
     			    rhsp->widthSignedFrom(newvarp);
     			    assignp->widthSignedFrom(newvarp);
     			    oldmodp->addStmtp(newvarp);
     			    oldmodp->addStmtp(assignp);
+    			}
+    		    }
+    		}
+    	    }
+    	}
+        }

         AstText*	m_baseTextp;	// Lowest TEXT node that needs replacement with varref
         AstVar*	m_varp;		// Variable we're under
         ImplTypedefMap	m_implTypedef;	// Created typedefs for each <container,name>
         AstModule*	m_topModule;	// The top-level module we are under
         // METHODS
         static int debug() {
-...
     	nodep->deleteTree(); nodep=NULL;
+        }
         virtual void visit(AstModule* nodep, AstNUser*) {
     	// Look for interfaces in the port list of the top-level module
     	if (nodep->level() == 2) {
     	    m_topModule = nodep;
+    	}
     	nodep->iterateChildren(*this);
     	m_topModule = NULL;
+        }
         virtual void visit(AstInterfaceDType* nodep, AstNUser*) {
     	if (m_topModule) {
     	    AstCell* cellp = new AstCell(nodep->fileline(), m_varp->name(), nodep->name(), NULL, NULL, NULL);
     	    cellp->hasVar(true); // We created the Cell from an existing Var
     	    m_topModule->addStmtp(cellp);
+    	}
+        }
         virtual void visit(AstNode* nodep, AstNUser*) {
     	// Default: Just iterate
     	checkExpected(nodep);  // So we detect node types we forgot to list here
-...
     	m_exp = AstParseRefExp::NONE;
     	m_baseTextp = NULL;
     	m_varp = NULL;
     	m_topModule = NULL;
     	rootp->accept(*this);
+        }
         virtual ~LinkParseVisitor() {}

     		// Note we allow multiple users of a parameterized model, thus we need to stash this info.
     		for (AstNode* stmtp=modp->stmtsp(); stmtp; stmtp = stmtp->nextp()) {
     		    if (AstVar* varp = stmtp->castVar()) {
     			if (varp->isIO() || varp->isGParam()) {
     			if (varp->isIO() || varp->isGParam() || varp->isInterface()) {
     			    // Cloning saved a pointer to the new node for us, so just follow that link.
     			    AstVar* oldvarp = varp->clonep()->castVar();
     			    //UINFO(8,"Clone list 0x"<<hex<<(uint32_t)oldvarp<<" -> 0x"<<(uint32_t)varp<<endl);

b/src/V3ParseImp.h
65	65	AstCase* casep;
66	66	AstCaseItem* caseitemp;
67	67	AstConst* constp;
	68	AstModportVar* modportvarp;
68	69	AstNodeModule* modulep;
69	70	AstNodeDType* dtypep;
70	71	AstNodeFTask* ftaskp;

     	m_scopep->addActivep(clonep);
     	clonep->iterateChildren(*this);	// We iterate under the *clone*
+        }
         virtual void visit(AstAssignVarScope* nodep, AstNUser*) {
     	// Copy under the scope but don't recurse, interfaces aren't linked yet
     	UINFO(4,"    Move "<<nodep<<endl);
     	AstNode* clonep = nodep->cloneTree(false);
     	nodep->user2p(clonep);
     	m_scopep->addActivep(clonep);
+        }
         virtual void visit(AstAssignW* nodep, AstNUser*) {
     	// Add to list of blocks under this scope
     	UINFO(4,"    Move "<<nodep<<endl);
-...
         virtual void visit(AstVar* nodep, AstNUser*) {
     	// Make new scope variable
     	if (!nodep->user1p()) {
     	    AstVarScope* varscp = new AstVarScope(nodep->fileline(), m_scopep, nodep);
     	    UINFO(6,"   New scope "<<varscp<<endl);
     	    nodep->user1p(varscp);
     	    m_scopep->addVarp(varscp);
     	    if (nodep->isInterface()) {
     		AstVarScope* varscp = new AstScopeAlias(nodep->fileline(), m_scopep, nodep, NULL);
     		UINFO(6,"   New scope alias "<<varscp<<endl);
     		nodep->user1p(varscp);
     		m_scopep->addVarp(varscp);
     	    } else {
     		AstVarScope* varscp = new AstVarScope(nodep->fileline(), m_scopep, nodep);
     		UINFO(6,"   New scope "<<varscp<<endl);
     		nodep->user1p(varscp);
     		m_scopep->addVarp(varscp);
+    	    }
+    	}
+        }
         virtual void visit(AstVarRef* nodep, AstNUser*) {
     	// VarRef needs to point to VarScope
     	// Make sure variable has made user1p.
     	nodep->varp()->accept(*this);
     	AstVarScope* varscp = (AstVarScope*)nodep->varp()->user1p();
     	if (!varscp) nodep->v3fatalSrc("Can't locate varref scope");
     	nodep->varScopep(varscp);
     	if (!nodep->varp()->isInterface()) {
     	    nodep->varp()->accept(*this);
     	    AstVarScope* varscp = (AstVarScope*)nodep->varp()->user1p();
     	    if (!varscp) nodep->v3fatalSrc("Can't locate varref scope");
     	    nodep->varScopep(varscp);
     	} else {
     	    nodep->varScopep(NULL);
+    	}
+        }
         virtual void visit(AstScopeName* nodep, AstNUser*) {
     	// If there's a %m in the display text, we add a special node that will contain the name()
-...
         virtual void visit(AstAssignAlias* nodep, AstNUser*) {
     	movedDeleteOrIterate(nodep);
+        }
         virtual void visit(AstAssignVarScope* nodep, AstNUser*) {
     	movedDeleteOrIterate(nodep);
+        }
         virtual void visit(AstAssignW* nodep, AstNUser*) {
     	movedDeleteOrIterate(nodep);
+        }

     	// else width in node is correct; it was set based on keyword().width()
     	// at construction time
+        }
         virtual void visit(AstInterfaceDType* nodep, AstNUser* vup) {
     	nodep->iterateChildren(*this, vup);
     	nodep->width(1, 1);
+        }
         virtual void visit(AstRefDType* nodep, AstNUser* vup) {
     	nodep->iterateChildren(*this, vup);
     	if (nodep->defp()) nodep->defp()->iterate(*this,vup);

     #include "V3GenClk.h"
     #include "V3Inline.h"
     #include "V3Inst.h"
     #include "V3Interface.h"
     #include "V3Life.h"
     #include "V3LifePost.h"
     #include "V3Link.h"
-...
         // Convert parseref's to varrefs, and other directly post parsing fixups
         V3LinkParse::linkParse(v3Global.rootp());
         // Link any new cells created from interfaces (empty filter)
         V3InFilter filter (v3Global.opt.pipeFilter());
         V3LinkCells::link(v3Global.rootp(), &filter);
         // Cross-link signal names
         V3Link::link(v3Global.rootp());
         // Cross-link dotted hierarchical references
-...
         V3LinkLValue::linkLValue(v3Global.rootp());
         v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("link.tree"));
         V3Error::abortIfErrors();
         if (v3Global.opt.stats()) V3Stats::statsStageAll(v3Global.rootp(), "Link");
         // Remove parameters by cloning modules to de-parameterized versions
-...
         // Must do this after we know the width of any parameters
         // We also do it after coverage/assertion insertion so we don't 'cover' the top level.
         V3LinkLevel::wrapTop(v3Global.rootp());
         v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("linklevel.tree"));
         // Lint interfaces
         V3Interface::lint(v3Global.rootp());
         v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("interface.tree"));
         // Propagate constants into expressions
         V3Const::constifyAllLint(v3Global.rootp());

       "do"			{ FL; return yDO; }
       "endclocking"		{ FL; return yENDCLOCKING; }
       "endpackage"		{ FL; return yENDPACKAGE; }
       "endinterface"	{ FL; return yENDINTERFACE; }
       "endprogram"		{ FL; return yENDPROGRAM; }
       "endproperty"		{ FL; return yENDPROPERTY; }
       "enum"		{ FL; return yENUM; }
-...
       "final"		{ FL; return yFINAL; }
       "iff"			{ FL; return yIFF; }
       "import"		{ FL; return yIMPORT; }
       "interface"		{ FL; return yINTERFACE; }
       "int"			{ FL; return yINT; }
       "logic"		{ FL; return yLOGIC; }
       "longint"		{ FL; return yLONGINT; }
       "modport"		{ FL; return yMODPORT; }
       "package"		{ FL; return yPACKAGE; }
       "priority"		{ FL; return yPRIORITY; }
       "program"		{ FL; return yPROGRAM; }
-...
       "dist"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "endclass"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "endgroup"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "endinterface"	{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "endsequence"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "expect"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "extends"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
-...
       "ignore_bins"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "illegal_bins"	{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "inside"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "interface"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "intersect"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "join_any"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "join_none"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "local"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "matches"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "modport"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "new"			{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "null"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
       "packed"		{ yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }

     %token<fl>		yENDCLOCKING	"endclocking"
     %token<fl>		yENDFUNCTION	"endfunction"
     %token<fl>		yENDGENERATE	"endgenerate"
     %token<fl>		yENDINTERFACE	"endinterface"
     %token<fl>		yENDMODULE	"endmodule"
     %token<fl>		yENDPACKAGE	"endpackage"
     %token<fl>		yENDPRIMITIVE	"endprimitive"
-...
     %token<fl>		yINITIAL	"initial"
     %token<fl>		yINOUT		"inout"
     %token<fl>		yINPUT		"input"
     %token<fl>		yINTERFACE	"interface"
     %token<fl>		yINT		"int"
     %token<fl>		yINTEGER	"integer"
     %token<fl>		yLOCALPARAM	"localparam"
     %token<fl>		yLOGIC		"logic"
     %token<fl>		yLONGINT	"longint"
     %token<fl>		yMODPORT	"modport"
     %token<fl>		yMODULE		"module"
     %token<fl>		yNAND		"nand"
     %token<fl>		yNEGEDGE	"negedge"
-...
     //  Blank lines for type insertion
     //  Blank lines for type insertion
     //  Blank lines for type insertion
     //  Blank lines for type insertion
     %start source_text
-...
     description:			// ==IEEE: description
     		module_declaration			{ }
     	//UNSUP	interface_declaration			{ }
     	|	interface_declaration			{ }
     	|	program_declaration			{ }
     	|	package_declaration			{ }
     	|	package_item				{ if ($1) GRAMMARP->unitPackage($1->fileline())->addStmtp($1); }
-...
     	//			// IEEE: interface_port_header port_identifier { unpacked_dimension }
     	//			// Expanded interface_port_header
     	//			// We use instantCb here because the non-port form looks just like a module instantiation
     	//UNSUP	portDirNetE id/*interface*/                      idAny/*port*/ rangeListE sigAttrListE	{ VARDTYPE($2); VARDONEA($3, $4); PARSEP->instantCb(CRELINE(), $2, $3, $4); PINNUMINC(); }
     		portDirNetE id/*interface*/                      idAny/*port*/ /* UNSUPP variable_dimensionListE*/ /* UNSUPP sigAttrListE */
     			{ $$ = new AstPort(CRELINE(),PINNUMINC(),*$3);
     			  $$->addNext(new AstVar($<fl>2,AstVarType(AstVarType::INTERFACE),*$3,new AstInterfaceDType($<fl>2,*$2))); }
     	//UNSUP	portDirNetE yINTERFACE                           idAny/*port*/ rangeListE sigAttrListE	{ VARDTYPE($2); VARDONEA($3, $4); PINNUMINC(); }
     	//UNSUP	portDirNetE id/*interface*/ '.' idAny/*modport*/ idAny/*port*/ rangeListE sigAttrListE	{ VARDTYPE($2); VARDONEA($5, $6); PARSEP->instantCb(CRELINE(), $2, $5, $6); PINNUMINC(); }
     	|	portDirNetE id/*interface*/ '.' idAny/*modport*/ idAny/*port*/ /* UNSUPP rangeListE sigAttrListE */
     			{ $$ = new AstPort(CRELINE(),PINNUMINC(),*$5);
     			  $$->addNext(new AstVar($3,AstVarType(AstVarType::INTERFACE),*$5,new AstInterfaceDType($3,*$2,*$4))); }
     	//UNSUP	portDirNetE yINTERFACE      '.' idAny/*modport*/ idAny/*port*/ rangeListE sigAttrListE	{ VARDTYPE($2); VARDONEA($5, $6); PINNUMINC(); }
     	//
     	//			// IEEE: ansi_port_declaration, with [port_direction] removed
     	//			//   IEEE: [ net_port_header | interface_port_header ] port_identifier { unpacked_dimension }
-...
     	//UNSUP	portDirNetE signingE rangeList '.' portSig '(' portAssignExprE ')' sigAttrListE	{ UNSUP }
     	//UNSUP	portDirNetE /*implicit*/       '.' portSig '(' portAssignExprE ')' sigAttrListE	{ UNSUP }
     	//
     		portDirNetE data_type           portSig variable_dimensionListE sigAttrListE
     	|	portDirNetE data_type          portSig variable_dimensionListE sigAttrListE
     			{ $$=$3; VARDTYPE($2); $$->addNextNull(VARDONEP($$,$4,$5)); }
     	|	portDirNetE yVAR data_type      portSig variable_dimensionListE sigAttrListE
     			{ $$=$4; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); }
-...
     //**********************************************************************
     // Interface headers
     interface_declaration:		// IEEE: interface_declaration + interface_nonansi_header + interface_ansi_header:
     	//			// timeunits_delcarationE is instead in interface_item
     		intFront parameter_port_listE portsStarE ';'
     			interface_itemListE yENDINTERFACE endLabelE
     			{ if ($2) { $1->addStmtp($2); $2->v3error("Unsupported: Interfaces with parameters"); }
     			  if ($3) $1->addStmtp($3);
     			  if ($5) $1->addStmtp($5);
     			  SYMP->popScope($1); }
     	//UNSUPP yEXTERN	intFront parameter_port_listE portsStarE ';'	{ }
+    	;
     intFront<modulep>:
     		yINTERFACE lifetimeE idAny/*new_interface*/
     			{ $$ = new AstInterface($1,*$3);
     			  $$->inLibrary(true);
     			  PARSEP->rootp()->addModulep($$);
     			  SYMP->pushNew($$); }
+    	;
     interface_itemListE<nodep>:
     		/* empty */				{ $$ = NULL; }
     	|	interface_itemList			{ $$ = $1; }
+    	;
     interface_itemList<nodep>:
     		interface_item				{ $$ = $1 }
     	|	interface_itemList interface_item	{ $$ = $1->addNextNull($2) }
+    	;
     interface_item<nodep>:		// IEEE: interface_item + non_port_interface_item
     		port_declaration ';'			{ $$ = $1; }
     	//			// IEEE: non_port_interface_item
     	//UNSUP	generate_region				{ $$ = $1; }
     	|	interface_or_generate_item		{ $$ = $1; }
     	//UNSUP	program_declaration			{ $$ = $1; }
     	//UNSUP	interface_declaration			{ $$ = $1; }
     	|	timeunits_declaration			{ $$ = $1; }
     	//			// See note in interface_or_generate item
     	|	module_common_item			{ $$ = $1; }
+    	;
     interface_or_generate_item<nodep>:  // ==IEEE: interface_or_generate_item
     	//			    // module_common_item in interface_item, as otherwise duplicated
     	//			    // with module_or_generate_item's module_common_item
     		modport_declaration			{ $$ = $1; }
     	//UNSUP	extern_tf_declaration			{ }
+    	;
     //**********************************************************************
     // Program headers
-...
     	|	generate_region				{ $$ = $1; }
+    	;
     modport_declaration<nodep>:		// ==IEEE: modport_declaration
     		yMODPORT modport_itemList ';'		{ $$ = $2; }
+    	;
     modport_itemList<nodep>:		// IEEE: part of modport_declaration
     		modport_item				{ $$ = $1; }
     	|	modport_itemList ',' modport_item	{ $$ = $1->addNextNull($3) }
+    	;
     modport_item<nodep>:			// ==IEEE: modport_item
     		id/*new-modport*/ '(' modportPortsDeclList ')'		{ $$ = new AstModport($2,*$1,$3); }
+    	;
     modportPortsDeclList<modportvarp>:
     		modportPortsDecl			    { $$ = $1; }
     	|	modportPortsDeclList ',' modportPortsDecl   { $$ = $1->addNextNull($3)->castModportVar(); }
+    	;
     // IEEE: modport_ports_declaration  + modport_simple_ports_declaration
     //	+ (modport_tf_ports_declaration+import_export) + modport_clocking_declaration
     // We've expanded the lists each take to instead just have standalone ID ports.
     // We track the type as with the V2k series of defines, then create as each ID is seen.
     modportPortsDecl<modportvarp>:
     	//			// IEEE: modport_simple_ports_declaration
     		port_direction modportSimplePort	{ $$ = new AstModportVar($<fl>1,*$2,GRAMMARP->m_varIO); }
     	//			// IEEE: modport_clocking_declaration
     	//UNSUP	yCLOCKING idAny/*clocking_identifier*/	{ }
     	//UNSUP	yIMPORT modport_tf_port			{ }
     	//UNSUP	yEXPORT modport_tf_port			{ }
     	// Continuations of above after a comma.
     	//			// IEEE: modport_simple_ports_declaration
     	|	modportSimplePort			{ $$ = new AstModportVar($<fl>1,*$1,AstVarType::INOUT); }
+    	;
     modportSimplePort<strp>:	// IEEE: modport_simple_port or modport_tf_port, depending what keyword was earlier
     		id					{ $$ = $1; }
     	//UNSUP	'.' idAny '(' ')'			{ }
     	//UNSUP	'.' idAny '(' expr ')'			{ }
+    	;
     //************************************************
     // Variable Declarations

     #!/usr/bin/perl
     if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
     # DESCRIPTION: Verilator: Verilog Test driver/expect definition
+    #
     # Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
     # redistribute it and/or modify it under the terms of either the GNU
     # Lesser General Public License Version 3 or the Perl Artistic License
     # Version 2.0.
     compile (
     	 v_flags => []
     	 );
     execute (
     	 check_finished=>1,
          );
     ok(1);
 ;

     // DESCRIPTION: Verilator: Verilog Test module
     //
     // This file ONLY is placed into the Public Domain, for any use,
     // without warranty, 2006 by Wilson Snyder.
     interface counter_io;
        logic [3:0] value;
        logic       reset;
     endinterface
     module t (/*AUTOARG*/
        // Inputs
        clk
        );
        input clk;
        integer cyc=1;
        counter_io c1_data();
        counter_io c2_data();
        counter    c1 (.clkm(clk),
     	      .c_data(c1_data),
     	      .i_value(4'h1));
        counter    c2 (.clkm(clk),
     	      .c_data(c2_data),
     	      .i_value(4'h2));
        initial begin
           c1_data.value = 4'h4;
           c2_data.value = 4'h5;
        end
        always @ (posedge clk) begin
           cyc <= cyc + 1;
           if (cyc<2) begin
     	 c1_data.reset <= 1;
     	 c2_data.reset <= 1;
           end
           if (cyc==2) begin
     	 c1_data.reset <= 0;
     	 c2_data.reset <= 0;
           end
           if (cyc==20) begin
     	 $write("[%0t] c1 cyc%0d: %0x %0x\n", $time, cyc, c1_data.value, c1_data.reset);
     	 $write("[%0t] c2 cyc%0d: %0x %0x\n", $time, cyc, c2_data.value, c2_data.reset);
     	 if (c1_data.value != 2) $stop;
     	 if (c2_data.value != 3) $stop;
     	 $write("*-* All Finished *-*\n");
     	 $finish;
           end
        end
     endmodule
     module counter
+       (
        input clkm,
        counter_io c_data,
        input logic [3:0] i_value
        );
        always @ (posedge clkm) begin
           if (c_data.reset)
     	 c_data.value <= i_value;
           else
     	 c_data.value <= c_data.value + 1;
        end
     endmodule : counter

     #!/usr/bin/perl
     if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
     # DESCRIPTION: Verilator: Verilog Test driver/expect definition
+    #
     # Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
     # redistribute it and/or modify it under the terms of either the GNU
     # Lesser General Public License Version 3 or the Perl Artistic License
     # Version 2.0.
     top_filename("t/t_interface.v");
     compile (
     	 # Avoid inlining so we find bugs in the non-inliner connection code
     	 v_flags => ["-Oi"],
     	 );
     execute (
     	 check_finished=>1,
          );
     ok(1);
 ;