| 95 |
95 |
V3SymTable m_mods; // Symbol table of all module names
|
| 96 |
96 |
LinkCellsGraph m_graph; // Linked graph of all cell interconnects
|
| 97 |
97 |
LibraryVertex* m_libVertexp; // Vertex at root of all libraries
|
|
98 |
V3GraphVertex* m_topVertexp; // Vertex of top module
|
| 98 |
99 |
|
| 99 |
100 |
static int debug() {
|
| 100 |
101 |
static int level = -1;
|
| ... | ... | |
| 126 |
127 |
vvertexp->modp()->level(vvertexp->rank()+1);
|
| 127 |
128 |
}
|
| 128 |
129 |
}
|
|
130 |
if (v3Global.opt.topModule()!=""
|
|
131 |
&& !m_topVertexp) {
|
|
132 |
v3error("Specified --top-module '"<<v3Global.opt.topModule()<<"' was not found in design.");
|
|
133 |
}
|
| 129 |
134 |
}
|
| 130 |
135 |
virtual void visit(AstModule* nodep, AstNUser*) {
|
| 131 |
136 |
// Module: Pick up modnames, so we can resolve cells later
|
| 132 |
137 |
m_modp = nodep;
|
| 133 |
138 |
UINFO(2,"Link Module: "<<nodep<<endl);
|
| 134 |
|
if (nodep->inLibrary()) {
|
|
139 |
bool topMatch = (v3Global.opt.topModule()==nodep->name());
|
|
140 |
if (topMatch) m_topVertexp = vertex(nodep);
|
|
141 |
if (v3Global.opt.topModule()==""
|
|
142 |
? nodep->inLibrary() // Library cells are lower
|
|
143 |
: !topMatch) { // Any non-specified module is lower
|
|
144 |
// Put under a fake vertex so that the graph ranking won't indicate
|
|
145 |
// this is a top level module
|
| 135 |
146 |
if (!m_libVertexp) m_libVertexp = new LibraryVertex(&m_graph);
|
| 136 |
147 |
new V3GraphEdge(&m_graph, m_libVertexp, vertex(nodep), 1, false);
|
| 137 |
148 |
}
|
| ... | ... | |
| 231 |
242 |
LinkCellsVisitor() {
|
| 232 |
243 |
m_modp = NULL;
|
| 233 |
244 |
m_libVertexp = NULL;
|
|
245 |
m_topVertexp = NULL;
|
| 234 |
246 |
}
|
| 235 |
|
virtual ~LinkCellsVisitor() {
|
| 236 |
|
}
|
|
247 |
virtual ~LinkCellsVisitor() {}
|
| 237 |
248 |
void main(AstNetlist* rootp) {
|
| 238 |
249 |
rootp->accept(*this);
|
| 239 |
250 |
}
|