Verilog-2001 style attributes (constraints)

Hi,

I'm trying to use Verilog-2001 style (* *) constraints, but the indentation gets screwed up. I'm using verilog-mode.el version 502

module example(out1, out2, out3);

   (* LOC = "D14" *)
  output          out1;
   (* LOC = "C15" *)
    output          out2;
   (* LOC = "C16" *)
      output          out3;

   out1 = 1'b1;
   out2 = 1'b1;
   out3 = 1'b1;
endmodule

Is there some way to make this work ?

Replies (1)

RE: Verilog-2001 style attributes (constraints) - Added by Wilson Snyder almost 3 years ago

Filed as bug95.

(1-1/1)