Verilog-mode

Hi again.

I've got a ton of signals and ports that are various typedefs/structs. When verilog-mode indents these, it doesn't recognize the types and doesn't indent them properly. For example:

typedef  logic [7:0] mytype1_s;  // cell pointer

typedef struct packed {
   mytype1_s aa;
   celloffset_s bb;
   logic       cc;
   logic       dd;
   logic       ee;
   } mystruct1_s;

module test_indent
    (
     input logic         clock,
     output logic [31:0] data_out,
     input               mystruct1_s p1, // NOT INDENTED CORRECTLY
     output              to_qram_rdarb_s [3:0] out_arry1, // NOT INDENTED CORRECTLY

     output logic        done
     );

endmodule // test_indent
// Local Variables:
// verilog-typedef-regexp: "_s$" 
// End:

Is there some way to let verilog-mode know about my data types? Something like what verilog-typedef-regexp does for AUTOs?

Thanks!

David