Verilog-mode

Hi, I've searched the docs and the wiki, but I can't figure out how to AUOTINST to a SV interface.

For example, given the following code:

------------------------------ my_sv_if.sv --------------------------------
interface my_sv_if
  logic a;
  logic b;
  modport master_mp(input a, output b);
  modport slave_mp(output a, input b);
  modport monitor (input a, input b);
endinterface

-------------------------------- my_tb.sv ---------------------------------
module my_tb;
  my_if inst_if (/*AUTOINST*/);
endmodule

---------------------------------------------------------------------------

verilog-mode will complain with the following error:

"verilog-modi-lookup: biu_tb.v:738: Can't locate my_if module definition
    Check the verilog-library-directories variable.
    I looked in (if not listed, doesn't exist):
    < some path >
    < some path /my_if.sv >" 

What is very weird is that if I change the declaration from declaration of my_sv.sv from 'interface' to module, then verilog-mode correctly maps the first port of the interface.

Am I missing something syntax wide to interface properly (ie, modport name/usage?), or are interfaces currently not supported?

Thanks in advance,

Luis Gutierrez

PS. I'm using version 629 of verilog-mode.