Can I use /*AUTOINST*/ to instantiate a VHDL model?

Can I use /AUTOINST/ to instantiate a VHDL model?

If yes, any special requirements to do that?

Replies (1)

RE: Can I use /AUTOINST/ to instantiate a VHDL model? - Added by Wilson Snyder about 1 year ago

No, but you can write a AUTOSHELL that will call a script you write to do something similar - IE read the pins of the VHDL model and print out an instantiation. If you do so, please consider contributing it back here!

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Verilog-mode

Replies (1)

RE: Can I use /*AUTOINST*/ to instantiate a VHDL model? - Added by Wilson Snyder about 1 year ago

Can I use /AUTOINST/ to instantiate a VHDL model?

RE: Can I use /AUTOINST/ to instantiate a VHDL model? - Added by Wilson Snyder about 1 year ago