instantiate modules in same file

How do I instantiate module in same file?

for example

module foo (/*AUTOINST*/ /*AUTOINPUT*/ /*AUTOOUTPUT*/ endmodule

module foo_1 (/*AUTOINST*/) /*AUTOINPUT*/ /*AUTOOUTPUT*/ foo i_foo (/*AUTOINST*/); endmodule

Thanks Sathi

Verilog-mode doesn't well support multiple modules in the same file, it's considered a bad practice; don't do it.

Thanks the reply. I will create a differetn file for the new module. Then I will "`include new_file.v" in the parent file.

Sathi

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