AUTOINST with naming convention that indicates input or output signals

Jacky Ma asked how to support naming conventions that add i_ for inputs of a block, and o_ for outputs of a block when using AUTOINST. The problem is that a signal name may need to change when the submodule's inputs are no longer inputs/outputs on the upper level.

Here's an example

module test (
   // Ports for module A
   input  i_A_outsidei,
   output o_A_outsideo,

   // Ports for module B
   input  i_B_outsidei,
   output o_B_outsideo );

   /*AUTOWIRE*/

   moduleA u0(
     /*AUTOINST*/
       // Note o_ and i_ added or stripped
              // Outputs
              .o_A_outsideo             (o_A_outsideo),
              .o_A_internal             (A_internal),
              // Inputs
              .i_A_outsidei             (i_A_outsidei),
              .i_B_internal             (B_internal));

   moduleB u1(
       /*AUTOINST*/
       // Note o_ and i_ added or stripped
             // Outputs
             .o_B_outsideo              (o_B_outsideo),
             .o_B_internal              (B_internal),
             // Inputs
             .i_B_outsidei              (i_B_outsidei),
             .i_A_internal              (A_internal));

endmodule

module moduleA (
    input  i_A_outsidei,
    output o_A_outsideo,

    input  i_B_internal,
    output o_A_internal
  );
  /*AUTOTIEOFF*/
endmodule

module moduleB (
    input  i_B_outsidei,
    output o_B_outsideo,

    input  i_A_internal,
    output o_B_internal
  );
  /*AUTOTIEOFF*/
endmodule

Replies (1)

RE: AUTOINST with naming convention that indicates input or output signals - Added by Wilson Snyder about 1 year ago

First, I'd suggest that naming conventions that change the signal name as it crosses the hiearchy aren't recommended. This convention is also going to cause great difficulty when moving towards SystemVerilog interfaces.

That out of the way, make a special function in your site's .emacs file as follows:

  (defun vl-site-i-o (basename)
        (cond ((assoc (concat "i_" basename)
                      (verilog-decls-get-inputs moddecls))
               "i_")
              ((assoc (concat "o_" basename)
                      (verilog-decls-get-outputs moddecls))
               "o_")
              ((assoc (concat "t_" basename)
                      (verilog-decls-get-inouts moddecls))
               "t_")
              (t "")))

Then call it in a template on the base signal name with i_ and o_ stripped:

   /* moduleA AUTO_TEMPLATE (
       .[iot]_\(.*\)    (@"(vl-site-i-o \\"\1\\")"\1[]),
     ); */

Also note Verilog-mode computes AUTOINPUT and AUTOOUTPUT after the submodule pins, so AUTOINPUT/AUTOOUTPUT won't work with this.

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