AUTOLOGIC / AUTOREGINPUT questions

Hi there.

I'm seeing a couple of things I don't understand.

First, I'm using logic instead of wire/reg everywhere. I use AUTOLOGIC and also have AUTOREGINPUT to catch inputs to modules I haven't finished yet. When I update autos, AUTOLOGIC is fine and AUTOREGINPUT declares the module inputs as type logic. However, when another guy in my group updates the same file, AUTOREGINPUT declares them as regs. I think we have the same emacs/verilog-mode/config. What would cause the difference? How does AUTOREGINPUT choose the signal type?

Also, there are some instantiated modules that use AUTOINST, but have some port listed before the AUTOINST line (yes - I'm working to use templates to avoid this). There's an output port after the AUTOINST line whose signal is showing up under AUTOREGINPUT instead of AUTOLOGIC. Any idea why?

Thanks!

David

Replies (1)

RE: AUTOLOGIC / AUTOREGINPUT questions - Added by Wilson Snyder 9 months ago

1. AUTOLOGIC sets verilog-auto-logic-type to "logic", which also affects later autos. Add setting that to your file and see if that solves it; see the example under the AUTOLOGIC help.

2. You perhaps are missing the "// Output" or "// Input" comment. BTW there's nothing wrong with putting signals before the AUTOINST, that can be better than a template in that typos (which would otherwise be unused template lines) will be detected.

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