Save variables from AUTO TEMPLATE and pass it to another script

I want to take all outputs of a module instantiation and generate a verilog code which will instantiate a library element on all the outputs automatically.

My approach

When instantiating a module i want to save vl-name, vl-dir, vl-width for a port in a data structure and pass it to another PERL script which i would call using AUTOINSERLISP. The perl script will generate the verilog code using the data structure. Is this possible? Could you please give an example?

Attached an example i tried to set a variable but i am not sure how to use it.

If my approach is incorrect please let me know how i can do this.

Thanks.

ex_inst.v (352 Bytes)

Replies (1)

RE: Save variables from AUTO TEMPLATE and pass it to another script - Added by Wilson Snyder 8 months ago

AUTOINST inserts one pin at a time, so this approach would be extremely inefficient.

There's a couple of alternatives; you could move your function to Lisp code, then call it in the template. That really would be best, and unless your script is huge will take less time than alternatives as lisp is a easy language to learn.

Or you could have your script parse an "MYAUTOINST" but this route is likely to be fairly complicated as you'd need a full parser. (You could use Verilog-Perl for example.)

A midway hack would be to have the AUTO_TEMPLATE for each pin print something like ".port(vl_name=NAME,vl_pin=NAME,etc=ETC)". Verilog mode will fill in the entire instantiation that way. Then have your AUTOINSERTLISP feed the buffer through a pipe to your program, where your program would convert the .port(vl_name...) to whatever you need.

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