Verilog-mode

Hi,

I found that I needed to "include" a group of signals for AUTOTIEOFF, rather than ignore them, and after spending several frustrating hours trying to craft an emacs regexp which did "all but", I gave up and hacked verilog-mode.el

Basically, I added a new variable, "verilog-auto-tieoff-include-regexp" and then change the code to call verilog-signals-matching-regexp if it's set instead of the old behavior.

Just curious if there is a better way... (and if not, is this a reasonable way to submit diffs? ;-)

-brad

+(defcustom verilog-auto-tieoff-include-regexp nil
+  "*If set, when creating AUTOTIEOFF list, include signals matching this regexp.
+See the \\[verilog-faq] for examples on using this." 
+  :group 'verilog-mode-auto
+  :type 'string)
+(put 'verilog-auto-tieoff-include-regexp 'safe-local-variable 'stringp)
+
...
@@ -11922,8 +11932,14 @@
                              (verilog-subdecls-get-interfaced modsubdecls)
                              (verilog-subdecls-get-outputs modsubdecls)
                              (verilog-subdecls-get-inouts modsubdecls)))))
-      (setq sig-list (verilog-signals-not-matching-regexp
-                     sig-list verilog-auto-tieoff-ignore-regexp))
+;;      (setq sig-list (verilog-signals-not-matching-regexp
+;;                   sig-list verilog-auto-tieoff-ignore-regexp))
+      (if verilog-auto-tieoff-include-regexp
+         (setq sig-list (verilog-signals-matching-regexp
+                         sig-list verilog-auto-tieoff-include-regexp))
+       (setq sig-list (verilog-signals-not-matching-regexp
+                       sig-list verilog-auto-tieoff-ignore-regexp)))
+;;