Verilog-mode

Seems reasonable; it's not trivial though because bind needs to act in the context of the module getting the instantiated added to, not the context with the AUTOBIND. But that's just whining, it's not too hard. Would you use it?

Oh, I see I misinterpreted the question. You're looking for an AUTOINOUT_WITH_EVERYTHING_AS_INPUT. Yes, that's trivial.

module ExampInst (o,i);
   output logic [31:0] o;
   input  i;

   InstModule instName
     (// Outputs
      .so    (o[31:0]),
      // Inputs
      .si    (i)
      /*AUTOINST*/);

   //bind InstModule Prog instProg
   //    (.si(si));

   // Note is based on context of caller
   bind InstModule Prog instProg
     (/*AUTOBIND*/
      .si      (si));

endmodule

module t;
   wire [31:0] o;
   ExampInst i
     (// Outputs
      .o    (o[31:0]),
      // Inputs
      .i    (1'b0)
      /*AUTOINST*/);

   Prog p (/*AUTOINST*/);

endmodule

Maybe not the best name, but I just uploaded AUTOINOUTIN:

program autoinoutin (
   /*AUTOINOUTIN("inst")*/
   // Beginning of automatic in/out/inouts (from specific module)
   input                lower_inb,
   input                lower_ina,
   input                lower_out,
   // End of automatics
endprogram

Implemented within hours! Wow.

That's great. Thanks a lot.

Leith