Verilog-mode

Hi.

I never got a response on my Issue I files 5 months ago ([[http://www.veripool.org/issues/386-Verilog-mode-Indenting-of-user-defined-data-types]], so I thought I'd try another angle.

How can I manually add my types in Verilog Mode?

I added some to verilog-keywords, which gets them highlighted, but not indented in declarations. I tried adding to verilog-type-font-keywords and verilog-type-keywords, but it didn't do anything (yes, I started a new emacs to make sure everything was re-read).

What do I change? Is in one place or all over the elisp?

Thanks!

David