Verilog-mode

Hi there!

I want to introduce a project I've been working on in my spare time. It is a Verilog IDE that runs within Emacs. It is written in Perl and utilizes the Verilog-Perl library and piggybacks onto Emacs verilog-mode, so I figure this is the perfect place to post :)

It is divided into 3 parts: verparse_server, verparse, and verparse.el. The verparse_server script runs as a daemon and builds a netlist with the Verilog-Perl module. It builds a Unix domain socket that allows for the client to communicate. Because of this, there is only Linux support at the moment. Next is the verparse script which passes requests to verparse_server. The final piece is the verparse.el Emacs lisp file that actually sends the verparse commands to the verparse_server.

When it is all up and running, it allows you from within Emacs to do the following things:

C-c C-w : Toggles the verparse module list buffer which contains a tree of all modules in the project. Clicking the mouse or using the Return key on a module will open the file with the module C-c C-f : Enter this when point is on a signal and point will move to where this signal is defined. C-c C-d : Enter this when point is on a define and the minibuffer will display the value of the define. C-c C-m : Enter this when point is on a module and point will move to where the module is defined. C-c C-j : Enter this within a submodule and point will move to where the submodule is instantiated. Currently this only works when the module is instantiated once in the project, but this will change soon.

I have many other features planned, but I think this is to the point where it is stable enough to use on a daily basis.

The project is hosted on github and you can clone it like this:

git clone http://github.com/zettawatt/VerParse.git Note: you must have git >= 1.7 for this to work

Or you can download a zip of the project by going here:

https://github.com/zettawatt/VerParse

For a detailed setup, run 'verparse_server --help' and follow the instructions under 'SETUP'. This will get you up and running with dummy verilog files contained in the project.

Let me know what you guys think. I am open to suggestions and volunteers!

Thanks, Chuck