backtick directives.

Hello, I recently upgraded to version 3.041 of Verilog-Perl from a very old version. My scripts now report errors on files that use the following directive: `suppress_faults `enable_portfaults `delay_mode_path `disable_portfaults `nosuppress_faults with this error:


%Error: sab_cgmx2_4x.v:10: Define or directive not defined: `suppress_faults
%Error: sab_cgmx2_4x.v:11: Define or directive not defined: `enable_portfaults
%Error: sab_cgmx2_4x.v:19: Define or directive not defined: `delay_mode_path
%Error: sab_cgmx2_4x.v:52: Define or directive not defined: `disable_portfaults
%Error: sab_cgmx2_4x.v:53: Define or directive not defined: `nosuppress_faults

Since my scripts use exit_on_error... nothing is getting done. So I used the celldefine directive as a template and added these into the source. Now the module understands them and my scripts work again. However, while I was well into the modifications I saw this in the code for VParse.h:

// The default behavior is to pass all unknown `defines right through.
// This lets the user determine how to report the errors.  It also nicely
// allows `celldefine and such to remain in the output stream.

This brings me to my question... How do I let Verilog::Perl know not to consider these directives as errors? And how can I ensure that things like suppress/enable are paired with nosuppress/disable like celldefine does without source mods?

One more question about t3... Eclipse seems to mangle the default indentation scheme as I edit and the test throw Bad indentation errors all over the place. Can these be ignored?

Thanks for the module by the way!

Nicky

Replies (4)

RE: backtick directives. - Added by Wilson Snyder over 4 years ago

Yes, all unknown defines are passed. You didn't say which parser you're using. If it's your error, you need to know to ignore them (perhaps I should provide an option so you don't need to think about it?), if it's the Netlist package file a bug referencing this and I'll fix it.

As for the spaces test, you can completely ignore it, though using Eclipse won't get you the time saving features of Verilog-mode for Emacs ;). Anyhow I suspect you're on windows? It's adding return endings. I'll disable that test for non-authors.

RE: backtick directives. - Added by Nicky Ayoub over 4 years ago

Here is my code fragment:

##########################################3
sub get_verilog_netlist {
    my ($Opt, @files) = @_;

    my $nl = new Verilog::Netlist (options => $Opt,
                   skip_pin_interconnect => 1,
                   link_read_nonfatal => 1,
                   );

    foreach my $file (@files) {
        $nl->read_file (filename=>$file);
    }
    # Read in any sub-modules
    $nl->link();
    $nl->lint();
    ###$nl->exit_if_error();

    return $nl;
}

I have to comment the $nl->exit_if_error() call in order for the scripts to work in the 3.041 version. Once I add my mods I can uncomment the call.

I have attached a patch for your review. I am not sure if my problem is a bug or if I am just not using the tool appropriately. In any case, explicitly adding the patch fixes my current issue... I don't know how many others it causes ;) You can have those 'at not extra charge!'

I'm not sure if there are some side effects that I am not considering. This is my first time looking into the code. So please handle with care.

Thanks again.

patch-add-backticks (24.7 kB)

RE: backtick directives. - Added by Wilson Snyder over 4 years ago

I'm going to add ignoring these to the next version. Your patch also parses them and passes them to the application, but I don't think anyone will use them (were you?) as they are listed as old Verilog-XL constructs that the couple of tools I checked ignore.

RE: backtick directives. - Added by Wilson Snyder over 4 years ago

The latest 3.043 release should fix this.

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