Trying to understand Verilog::Preroc

I'm having trouble understanding how to get Verilog::Preproc working.

I've extended the Verilog::Parser class/package and was able to override the 'define' method such that it was called as expected when parsing a file.

But when I do that, the file is not parsed correctly in that it doesn't use the proper `define values later in the code. If I don't override the 'define' method, then it seems to parse correctly.

Am I supposed to return some particular value for the 'define' method ? I've tried to return '1' and the 'value' argument, with no difference.

And I was not able to get 'def_exists' called, even though I have an `ifdef in my example. Is that not when that will be called?

All I really want to do is parse through several files and report the value of all `defines at the end. I don't want to modify the parsing in any way, I just want the final result.

It seems I'm supposed to maybe maintain a table of the `defines, getting updates and queries from the parser as it encounters `defines and `ifdef's, etc. Is that true? I don't see that described explicitly anywhere in the docs. Is there maybe an overview page somewhere in the man pages that I'm missing?

Here's my extended Verilog::Preproc:

package MyProc;
use Verilog::Getopt;
use Verilog::Preproc;
use base qw(Verilog::Preproc);

sub define {
   my $self = shift;
   my ($defname, $value, $params) = @_;
   $defines{$defname} = $value;
}

sub def_exists {
   my $self = shift;
   my ($defname) = @_;

   print "def_exists: $defname\n";
   return 1 if exists $defines{$defname};
   return 0;
}
1;

Then I just spin though the Verilog code by calling $vp->getline() as per the README.

Here's my simple input file:

`define XXX 123
`define FUD

module foo(
      input x
      );

parameter Y = 2;

`ifdef FUD
wire fud;
`else
wire no_fud;
`endif

endmodule

The output of the parser as shown includes 'wire no_fud', even though FUD is defined.

Note that Modelsim compiles this without problem.

If anyone could help me out with this, I'd appreciate it. I'm afraid I know very little about OOP Perl, so that may be half the problem.

Thanks Tom

Replies (1)

RE: Trying to understand Verilog::Preroc - Added by Gene Sullivan over 1 year ago

If all you really want is a list of defines, I see no need to extend Verilog::Preproc. You can just access the has of defines from the $vp object. To view the contents of the object, you can use [[http://perldoc.perl.org/Data/Dumper.html]].

use warnings;
use strict;
use Verilog::Preproc;
use Data::Dumper;

$Data::Dumper::Sortkeys=1; 

my $vp = Verilog::Preproc->new();
$vp->open(filename => 'foo.v');
$vp->getall();
my %defines = %{ $vp->{options}->{defines} };
print Dumper(\%defines);

Here is the output:

$VAR1 = {
          'FUD' => '',
          'XXX' => '123'
        };

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