Verilog-Perl

Not currently. Generally I make a hash and load it.

The caution here is that Verilog-Perl doesn't parse the expressions in port interconnects, nor logic connecting two signals, so it may not be of great use in following interconnect.

Hi,

We've added a few lines of code to verilog-perl to give the above lists (should we share it on the forum? Though I feel it is fairly simple and straight-forward), and yes it would be nice if we could traverse across logic expressions as well. Is this possible through Verilator? We have figured that there is a struct called AstNode which gets created for each logic expression, and there is a struct called AstVar which gets created for each variable. If we can get all of the AstVars that each AstNode connects together, we may be able to figure out a lot more about the design connectivity. Can you please tell us whether this understanding of the situation is correct? And if so, is there a convenient way to figure out all of the AstVars connected to an AstNode?

Thanks for all your help ..............

Yes, Verilator has that information. Many of the "Visitor" classes do what you're looking for. Generally they build a connectivity graph specialized for whatever purpose, commonly with Vars and logic (often statement) as graph nodes, and connected by vertexes. V3Gate and V3Cdc are some examples of this after the design is flat.

If you add code to dump some generic format (XML for example) that describes the interconnect, I'd be willing to take it back.

BTW depending on your constraints, another alternative may be to use the VPI with a commercial simulator, and traverse it at startup time.

If you haven't already you might want to read "Which Parser Package" under Verilog-Perl: WHICH PARSER PACKAGE?

Wow, I'm glad to see there is recent activity here. I'm just starting a project parsing some Verilog and this is the exact feature I need!

Gautam, would you mind sharing the code you mentioned? What I've been doing so far is basically the same as what's done in Verilog::Netlist::Net->dump_drivers, but it is very inefficient and slow. I know that I need to build up some sort of structure so I don't need to iterate over the entire set of pins for each net in the design, but pretend that I'm an Electrical Engineer and don't quite know what "make a hash and load it" means :-)

I'm dealing with strictly a netlist, without any busses or logic expressions that need to be parsed.

What I've done so far is added a few lines of code, which I will list below. I've modified only 3 files: Net.pm, Port.pm and Pin.pm

I shall put the added lines of code with respect to the version I downloaded about 10 days ago, i.e. Verilog-Perl-3.230. I shall indicate the line numbers and give two lines before and after the modified code.

           _used_out    => '$', #'      # Receiver count on signal
           _used_inout  => '$', #'      # Bidirect count on signal
           connected_ports_list => '@', #'      # Ports connected to this net
           connected_pins_list => '@', #'       # Pins connected to this net
           # SystemPerl only: below only after autos()
           simple_type  => '$', #'      # True if is uint (as opposed to sc_signal)

Net.pm: after line 140 (i.e. after having added the above two lines)

sub _used_inout_inc { $_[0]->_used_inout(1+($_[0]->_used_inout()||0)); }
sub stored_lsb { defined $_[0]->SUPER::stored_lsb ? $_[0]->SUPER::stored_lsb : $_[0]->lsb; }

sub _add_connected_port { push(@{$_[0]->connected_ports_list}, $_[1]); }
sub _add_connected_pin { push(@{$_[0]->connected_pins_list}, $_[1]); }

sub connected_ports { return(@{$_[0]->connected_ports_list}); }
sub connected_pins { return(@{$_[0]->connected_pins_list}); }

sub width {
    my $self = shift;
    # Return bit width (if known)

elsif ($dir eq 'out')   { $self->net->_used_out_inc(); }
        elsif ($dir eq 'inout') { $self->net->_used_inout_inc(); }
        $self->net->_add_connected_pin($self);
    }
}

$self->net->_used_out_inc()   if ($self->direction() eq 'in');
        $self->net->_used_inout_inc() if ($self->direction() eq 'inout');
        $self->net->_add_connected_port($self);
    }
}

Then of course you have to go through the "make" process again. Once you have done that, you will get two routines: Net::connected_ports() and Net::connected_pins()

which can be used exactly as you would use "Module::nets()" to get all of the nets within a module.

I have tested these out only on limited cases, so I hope nothing goes wrong.