Verilog-Perl

Hey,

found a syntax checking bug that causes the netlist reader to bomb out with an error.

If I declare a 2d array as

wire [7:0] array [2];

then I get a syntax error. But if I use

wire [7:0] array [0:1]

then all is well.

The error is: %Error: my_file.v:232: syntax error, unexpected ']', expecting ':' Exiting due to errors

Thanks, Shareef.