Verilog-Perl

Call

  print $module_object->verilog_text

You'd then print to a file handle if you want it in a file, perhaps to the $module_object->filename to return it to where it came from.

Couple of questions

a) my source file was Verilog-2001 with ANSI-style declarations... when I

open (OUT_FILE,">$newfile.tmp");
      map {
          printf OUT_FILE $_;
      } ($mod->verilog_text);
      close (OUT_FILE);

I don't get any input/output declarations..

b) does it keep the comments anywhere? I am not seeing any of the comment text from the original file in the resulting file (from the print above)

thanks, Mike

a) That should work. Maybe the objects weren't created? Try printing $netlist->dump to see if the structures are what you think they should be.

  $netlist_object = Verilog::Netlist->new(...., keep_comments=>1);

netlist->dump shows the list of ports with directions.

input file has

module s0a ( output wire CLK_DBG_S0);

output file has

module s0a ( CLK_DBG_S0A ); wire CLK_DBG_S0A;

but nowhere does it declare it as an output.

I added your module to a test, and write_verilog correctly creates:

module msg328 (
   msg328w);
   output msg328w;
endmodule

Are you using the most recent version? If so, can you package up a test case and file a bug?

Filed... Issue #278