How to preserve the order of input file?

I used $nl->read_file to read in one netlist and then do some modification such as delete all nets of one cell. After that, I tried to save the modified netlist by printing $nl->verilog_text to the new file. It seems the order of modules and ports inside the new netlist has changed. For example, in old netlist, module A is defined after module B. But in modified netlist, the order of module A and B will be swapped. In other words, the modules in output file are in alphabetical order. I'd like to keep the order of input file. Not sure whether there is some methods to achieve this goal.

Replies (3)

RE: How to preserve the order of input file? - Added by Wilson Snyder over 1 year ago

There isn't a current function to do this, but you can write a function yourself that iterates sorting by line number, instead of alphabetically.

RE: How to preserve the order of input file? - Added by Miranda Zhang over 1 year ago

I see. Also the default output will merge all ports of one module to one line regardless of the input format. Any method to avoid this?

RE: How to preserve the order of input file? - Added by Wilson Snyder over 1 year ago

Again, write a custom outputter that looks at the lineno and inserts lines as needed.

If you're really intent on maintaining the input formatting, you may be better off using Verilog::Parser to recognize the code on the fly - you can then keep everything including whitespace. See vpassert for a program that does this.

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