Syntax Errors using Packed Structures

I'm trying to parse a standalone RTL file which has the following line of code in it:

dps_t dps_a, dps_b, dps_c;

Here, dps_t is a typedef'd packed structure, however, I have not defined it in my RTL. During the preprocessing of my RTL, I am getting an error which says " %Error: dpiounit.v:291: syntax error, unexpected ',', expecting '(' " where line 291 is the above line of code. I think what is happening here is that the parser thinks I am trying to instantiate a unit so it expects a '(' after dps_a is declared.

Does anyone have a workaround? (e.g. Any way I can tell the parser to ignore this?)

Thanks, Ritesh

Replies (2)

RE: Syntax Errors using Packed Structures - Added by Wilson Snyder over 1 year ago

Verilog-Perl (along with any other compiler) needs to see the definition of dps_t. Presumably there's an include missing?

Unfortunately there's no way to parse SystemVerilog without this information.

RE: Syntax Errors using Packed Structures - Added by Ritesh Patel over 1 year ago

Thanks for the info. I was trying to parse it without including the file, but I guess I have to include it.

Thanks, Ritesh

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