Verilog-Perl

Strangely bug153 didn't indicate that the resolution was that it's the user's job to evaluate. I fixed that.

Doing better is a long term goal....

I am experiencing a similar issue. But in this case the expression is more complicated like: WIDTH-1

where width is a parameter. If the parameter is defined in the module declaration then I can look it up. I used the dump tests to figure this out:

module v_v2k

1. ( input clk, input rst, input [WIDTH:0] sig1, output reg [WIDTH:0] sig2 );

But if I change the syntax a little I can't figure out how to reference the top level parameter (net) and I loose it:

parameter WIDTH = 16;

module v_v2k_mchp
 (
  input clk,
  input rst,
  input [WIDTH:0]      sig1,
  output reg [WIDTH:0] sig2
 );

~/src/perl/verilog/Verilog-Perl$ diff -c test_dir/42_v2k.dmp t/42_dumpcheck_v2k.out

• test_dir/42_v2k.dmp 2011-09-16 16:09:56.144532000 -0700 --- t/42_dumpcheck_v2k.out 2011-09-16 15:15:45.348560000 -0700 *******
• 3,8 ** --- 3,9 ---- Port:rst Dir:in DataT: Array: Port:sig1 Dir:in DataT:[WIDTH:0] Array: Port:sig2 Dir:out DataT:reg [WIDTH:0] Array: + Net:WIDTH DeclT:parameter NetT: DataT: Array: Value:16 Net:clk O DeclT:port NetT: DataT: Array: Net:rst O DeclT:port NetT: DataT: Array: Net:sig1 O DeclT:port NetT: DataT:[WIDTH:0] Array: WIDTH:0 nicky@hoser:~/src/perl/verilog/Verilog-Perl$

Do you really mean you put WIDTH above the module declaration? That's legal SystemVerilog, but unusual and not what's normal.

Assuming not, you can $module->find_net("WIDTH") and use the found $net->value.

Yes, the parameter is declared above the module declaration and as you state is legal in SV but is not normal... So, I am assuming that WIDTH is not available as a net at the top level. I can see if we can change the source verilog and move on.

Thanks