error with multiple begin/end in the same generate loop

I was trying to read in a file (code re-use) and got an error.

the file had structure such as

generate
begin: block1
end
begin: block2
end
begin: block3
end
endgenerate

I got the error to go away by changing it to generate begin: block1 end endgenerate generate begin: block2 end endgenerate generate begin: block3 end endgenerate

Replies (2)

RE: error with multiple begin/end in the same generate loop - Added by Wilson Snyder over 1 year ago

My reading of the Verilog language grammar is this is illegal; begin can only follow a generate if/for/case, but it seems odd the simulators take it. I've asked the SV committee for clarification.

RE: RE: error with multiple begin/end in the same generate loop - Added by Wilson Snyder over 1 year ago

It's a bug with the other simulator(s).

Subject: Re: [sv-bc] Generate with multiple begins

From: Brad Pierce <...>

Verilog-2005 prohibits standalone generate begin-end blocks, regardless of whether they are nested. It is definitely not an oversight in the BNF. The restrictions were added on purpose to Verilog-2005.

I can well believe that some simulators are still not enforcing the generate restrictions of the Verilog-2005 standard, upon which SystemVerilog-2005 depends, and which was merged into SystemVerilog-2009. But that is an issue to take up with the simulator vendors. The LRM is clear.

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