Verilog-Perl

Hello all,

I a design automation engineer posed with the following problem. When compiling and elaborating a GLS model (mix of RTL and gate-level netlists) we see a lot of XMRE (cross module reference errors) in VCS. These errors are due to wires being probed in the testbench that no longer exist in the gate-level netlist. These wires were optimized away or renamed by the synthesis tool and no longer exist in the netlist. It is very painful for the validation engineer to manually update the testbench with the correct probe statement.

The solution I proposed was to disallow probing of internal wires in all testbenchs and only allow probing of ports. This is more of a methodology problem, however I was wondering if Verilog-Perl can be used to sanity check the test bench code prior to checking in.

At a high level, I would parse test bench and look for all assign statements. For each assign statement I would check to ensure that a port was being probed or else error out.

1.) Can verilog-perl be used to parse test bench code? 2.) Any high level examples you can point me to as which Verilog-Perl package I should use 3.) Any other suggestions?

Thanks,

Phil