Verilog-Perl

Yes, make a Verilog::Preproc object then call $parser->parse_preproc_file. See for example t/35_sigparser.t in the distribution.

Thanks for the quick reply! I really appreciate it.

For my purpose of parsing, I don't care what marco definitions are, but rather want to get the macro name itself. So, from my example above, I need to get $array=[`WIDTH] (or [WIDTH]) not 1:0 (if `define WIDTH 1:0 in some definition file). It seems like the best that I can do (so far) is, to create my own Preproc and rewrite the def_value callback as

sub def_value { # Return value my $self = shift; my $macro_name = shift; my $macro_definition = $self->{options}->defvalue_nowarn($macro_name); #printf "DEFVALUE @_ > %s\n", $self>{options}->defvalue_nowarn(@_); #return $self->{options}->defvalue(@_); my $return_val = $macro_definition =~ m{\d+:\d+} ? "__MACRO__$macro_name:__MACRO__$macro_name" : $macro_definition ; return $return_val; }

and retrieve macro name from "__MACRO__xxxx:__MACRO__xxxx". What a ugly hack, sorry best that I can come up with so far :-p Can you think of a better way?

Thanks, DK

I think that's the best route.

Ahrrr, cannot make parser to ignore undefined macros.

If there is a macro that is not defined hence left unsubstituted by preproc, parser flags an error. For example, parsing a port declaration below,

input [`UNDEFINED_MACRO] foo,

parser got to [ and Verilog::Parser::operator is called (following the perl debugger). The next thing I see from debugger is Verilog::Parser::error is called probably because parser doesn't like `XXX after [ ? I guess in general dealing with unsubstituted macro in parser is impossible since the macro definition can be pretty much anything. But, just for bus declaration, if undefined macro is seen within [ ], can var or port be called with $array input of [`XXX]? :-p Please please consider the option otherwise I have to make my own very very very poor and limited parser for myself instead of using SigParser :-(

You certainly can't deal with the general case of defines being anything, presumably that's ok for your application.

A further possible hack is to have your custom preproc always indicate that a macro is defined. If you do that, you'll also need to suppress the "redefining macro" warning.

Another route is to use the keyword parsing and do the higher levels yourself, this is what vppreproc does.

Finally, you might want to consider if you can change the Verilog code to use parameters instead, since parameters are what are supposed to vary between module usages.