Verilog-Perl

Given the structural & no concats & presumably no cell arrays etc, yes it can do this. Someone probably has, but I don't have an example.

You'd just need to iterate on each cell recursively, building a cell scope ("top.foo") then in that routine loop over each signal putting into a hash everything that connects. At pins you'd connect the hashes of the submodule and module together ("top.sub.pin" -> "top.signal_from_pin"), then recurse over the signal hash to print your report.

I'm not quite sure what all that means yet, but I'm sure it will help once I get started.

While I'm waiting for IT to get the package installed, I have a question about the Verilog options. Does Verilog::Netlist parse the standard command line options, such as -f and -v and define? (you show -y and and incdir, so I'm hoping it does).

I'm not sure how to get the file reading started if all my files come from the -f filelist option.

Typically I use a command like verilog -f filelist.f and it all happens automagically.

Thanks for the help.

You can install it yourself, see Installing.

Then download the kit and look at the Verilog::Getopt manpage and the t/41_example.t file.

I don't have root access, and didn't want to mess with setting it up otherwise, so I waited for IT to do it.

I'm trying to parse a large design just to better understand the limitations of the tools. It seemed to do very well.

parameter tpw_PGM = 25000.0:50000.0:100000.0; 
%Error: ../../../design/otp/rtl/slp/vlg/slp_tsmc180g33_8kx8_cm16d_ae.v:63: syntax error, unexpected ':', expecting ';'

I haven't started traversing yet.

Thanks

I'm playing with the show_hier example in Verilog::Netlist. I'm a bit confused regarding the best way to eliminate modules with `celldefine from the report. I can see that there is a callback in Verilog::Parser, and also in Verilog::Preproc.

If I decided I wanted to use the callbacks from Verilog::Parser (for that or any other reason), would I have to parse each file in addition to the parsing already done by Verilog::Netlist? Or is there a way to get those callbacks through Verilog::Netlist.

Thanks

I got the preproc define callback to work. I guess I went down the wrong path since the define callback won't help me with `celldefine. Can you point me in the best direction to determine which modules have `celldefine when using Verilog::Netlist?

Thanks

$module->is_libcell will be set if it's inside a `celldefine. Sorry it seems to be missing from the docs, I'll add it.