'always' block parser

'always' block cannot be parsed easily using Verilog::Parser. Will it be added to Verilog-Perl in the near future. Does anyone knows an elegant way of parsing 'always' blocks using Perl ( and extract its inputs/outputs and sensitivity list )

Replies (3)

RE: 'always' block parser - Added by Wilson Snyder 10 months ago

The parser handles the full language (minus a few bugs). What exactly is your problem?

RE: 'always' block parser - Added by Raz From 10 months ago

Thanks for the quick response, I'd like to extract inputs/outputs/sensitivity list, from an 'always' block, (a hash result is preferred). I've tried Verilog::Parser, and couldn’t find an easy way to do that

RE: 'always' block parser - Added by Wilson Snyder 10 months ago

I see, BTW I presume you mean the SigParser, not the Verilog::Parser.

Unfortunately you're right the SigParser doesn't present signal information from always blocks. Getting a simple text list might be possible but knowing what is an input or output from an always requires full elaboration and a lot of processing that isn't there at present, as you can have for loops and similar inside. Also sensitivity lists can be just @*. See the other options that elaborate under the "Which Parser" section of the manual.

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