Verilog-Perl

Without getting in to a long explanation, I am looking for a way to obfuscate the names in a design.. I had been considering doing it at the EDF level (FPGA), but I wondered if it might be simpler to parse the RTL.

At a 10,000 foot view, I would load the entire design.. ~ 40 files.. link it.. then wondering if I can go and walk thru every module.. change port names.. then signal names, and maybe even module names... not sure if I'd have to re-link along the way, and then spit out the modified code.

looking for feedback as to whether this seems possible (and practical)

thanks!