Verilator no make rule to make the Vfull_adder_ALL.a

Added by Adolfo Sanchez over 2 years ago

I was trying to make a VPI Interface with systemc usign Verilator. The Verilog model is a simple 4-bits full adder. I've installed Verilog-Perl, SystemPerl and Verilator and I've created all the Environment Variables, Following the manual I use this command:

$VERILATOR_ROOT/bin/verilator -sc full_adder.h

But when I enter to the new obj_dir folder to end the process and I type this:

make -f Vfull_adder.mk Vfull_adder_ALL.a

I get an error saying "No make rule to make the target Vfull_adder_ALL.a I'will attach the code of the Vfull_adder.mk and also the Verilog code

Thanks

P.S: S

full_adder.v - This is the verilog model of the full adder (286 Bytes)

Vfull_adder.mk - This is the generated .mk (661 Bytes)

Replies (1)

RE: Verilator no make rule to make the Vfull_adder_ALL.a - Added by Wilson Snyder over 2 years ago

It's Vfull_adder__ALL.a There's two underscores, in some fonts it looks like one. (It's two as there could be a module with _ALL in the name!)

Sorry for the trouble.

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