Bitwise check

Hello Verilator Experts,

I'm trying to verify a translated FIFO (to C++) with the original one (Verilog) and get differences at the cycles in which the fifo_full and fifo _empty are risong (one cycle difference). Is this a valid test? How do I make it 100% matching?

Thanks, Nadav.

Replies (1)

RE: Bitwise check - Added by Wilson Snyder almost 2 years ago

Is the test bench identical in both cases?

Maybe you have a race? If it's C++ and not SystemC it's really easy to read the new value of a signal when you expect the old value, or vice-versa. An easy fix is to run the testbench driver and monitors on the negative edges.

Anyhow it's hard to know without all the code (and that doesn't mean post it ;) Turn on traces, and add some prints of the values involved, and it will probably become apparent.

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