Efficient Usage of Verilog-Parameters

Added by Stefan Wallentowitz almost 2 years ago

Hi,

is there any efficient way of using verilator parameters? For my SystemC-Module I would like to instantiate multiple blocks of a module, each with a parameter. My solution: I make the parameter explicit via a register or wire. Then I inherit from the SystemC module and add a constructor that has the parameter and sets this wire.

Is there a better way, that I miss for the moment? Since my approach has an impact on my original verilog code, it would be nice to have such an option in verilator.

Thanks, Stefan

Replies (1)

RE: Efficient Usage of Verilog-Parameters - Added by Wilson Snyder almost 2 years ago

Sorry, there's no other way to do this, and it's rare enough that I don't want to add it at this time, but if you want to make a patch I'll consider it.

IMHO, if the parameter can be made a wire it probably should be a wire. The general intent of parameters is to vary the width and size of things. (And if it does need to vary the size, then it must be known at compile time.)

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