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Forums » Usage »

Access Register Without Defining as Input or Output

Added by Dan Snyder over 1 year ago

I'm having trouble accessing a register in my top module. I want to access all registers in my parent module which is one level below my c++ test bench. Is there a way to do this? I was unable to ascertain this from the documentation. Here is what I mean:

c++ file (sim_main.cpp):

 ...
*int a  = top->M;*
 ...

top module (MIPS.v):

module MIPS(x,y,z)
output x;
input y;
input z;

reg M;
 ...
endmodule

This will give me the following error:

error: ‘struct VMIPS’ has no member named ‘Status’ make: *** [sim_main.o] Error 1

Is this sort of access allowable? If so, what us the syntax to do such a thing?


Replies (7)

RE: Access Register Without Defining as Input or Output - Added by Dan Snyder over 1 year ago

Sorry for the poor posting form, feel free to ask for a re-post if it's unreadable.

RE: Access Register Without Defining as Input or Output - Added by Dan Snyder over 1 year ago

I tried the following referencing you're suggestion:

In C++ file: "int a = top->Status;"

In Verilog file MIPS.v within module MIPS: "reg [32:0] Status /*verilator public*/;"

Giving the following error: "error: ‘struct VMIPS’ has no member named ‘Status’ make: *** [sim_main.o] Error 1"

Any ideas?

RE: Access Register Without Defining as Input or Output - Added by Wilson Snyder over 1 year ago

There's another level of hierarchy Verilator adds. Use top->v->Status.

RE: Access Register Without Defining as Input or Output - Added by Dan Snyder over 1 year ago

Ah, I see. Following that change I got the following errors:

_"../sim_main.cpp:131: error: invalid use of incomplete type ‘struct VMIPS_MIPS’ ./VMIPS.h:13: error: forward declaration of ‘struct VMIPS_MIPS’"_

Is there something syntactic that I'm missing?

Also, if I wanted to access a register or wire from one module below my parent module would I use the command: "top->v->v->Status;"?

RE: Access Register Without Defining as Input or Output - Added by Wilson Snyder over 1 year ago

You need to #include the header generated for each module, from the top down to the final module you're accessing. Search for public in the test_regress directory for some examples.

Also, if I wanted to access a register or wire from one module below my parent module would I use the command: "top->v->v->Status;"?

Well top->v->subname->Status, yes.

It really is much nicer to make a DPI function to get at stuff.

RE: Access Register Without Defining as Input or Output - Added by Dan Snyder over 1 year ago

Got it, thanks, I'll definitely look into that. For the time being I just needed a quick way to do this to slap together a simple test.

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