Issues with dual clock domains?

Hi. We've been having some issues with a design using dual clock domains. We've been seeing occasional simulation failures with the Verilator model that do not show up using other simulators (typically, incorrect data output). The failures do not occur if the two clocks are driven at the same rate from the Vera environment.

Before spending more time investigating the issue, I'm wondering if there are any known things to look out for when using Verilator with designs using multiple clock domains? Any suggested approaches to debugging?

Thanks.

Replies (2)

RE: Issues with dual clock domains? - Added by Wilson Snyder over 1 year ago

Assuming a synthesizable design, the big gotchas are gated clocks, as described in the FAQ part of the manual. Also, there's one known bug, bug265, which is waiting for a testcase.

Beyond that, the typical debug pattern is to capture waves with a good simulation, then the bad one. Compare with a tool or visually to determine the first flop that goes bad. Then look at the source code that generates that signal, adding printf's as needed. Also you may want to compile your model with VL_DEBUG then call Verilated::debug(9) and it will print all events as they occur.

RE: Issues with dual clock domains? - Added by Wilson Snyder over 1 year ago

Oh also, I'm sure you already checked this, but if your code has Verilog races you will get different results, as the order of events isn't specified. I'm assuming your code lints cleanly so this isn't the issue.

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