Tracing SystemC and verilated Verilog together

Added by Chandan Egbert about 1 year ago

I have a test environment written in SystemC and I run Verilator to convert my RTL to SystemC. I would like to dump signals from the test bench and the RTL into the same vcd file so that I can use gtkwave effectively. Is there a way to do this?

Alternatively, does anyone know of a free or GPLed tool that can merge two vcd files?

Thanks in advance.

Replies (2)

RE: Tracing SystemC and verilated Verilog together - Added by Wilson Snyder about 1 year ago

There is not a way at present to do that, unless you use SystemPerl which has merged tracing.

I don't know of a tool to merge VCDs, it wouldn't be too hard to make one though. Note though many waveform viewers have a way to read multiple files and view them together, so you might not need to merge them at all.

RE: Tracing SystemC and verilated Verilog together - Added by Chandan Egbert 11 months ago

The SystemPerl solution works very well. In addition, it makes it much easier to write my SystemC. Thanks!

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