Problem while compiling my VERILOG-A code

Hi all,

I'm new to the topic programming VERILOG. I write already the first few examples (Adder, MUX) and they worked bretty well. But now I tried to write the Angelove model in VERILOG-A (to simulate some transistors) and have a problem when I compile my files. Verilator said the following when I try to compile my code:

%Error: current.v:4: Unsupported: Verilog 1995 reserved word not implemented: real
%Error: current.v:4: syntax error, unexpected ';', expecting IDENTIFIER
%Error: current.v:5: Unsupported: Verilog 1995 reserved word not implemented: real
%Error: current.v:6: Unsupported: Verilog 1995 reserved word not implemented: real
%Error: current.v:7: Unsupported: Verilog 1995 reserved word not implemented: real
%Error: current.v:8: Unsupported: Verilog 1995 reserved word not implemented: real
%Error: Cannot continue
%Error: See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed verilator_bin --language 1364-2001 -prefix main -Wall --cc current.v our.v

So far I understand that, the compiler didn't know the 1364-2001 standard but I gave him the command "--language 1364-2001" so he should know at least the key word "real". Did I make something wrong? Or maybe I compile Verilator in a wrong way ? How I install verilator: I've downloaded the newest version and compiled it how it stands in the readme(./configure , make , make test_c, sudo make install). So I think this should be find. Maybe it was wrong to compile Verilator without SystemC ?

By the way the Angelov model needs hyperbolic tangent so I need at least the 1364-2001 standard.

I hope somebody can help me, thanks.

regards, Robert

PS: I have a Ubuntu 10.04 64-bit and gcc 4.4.3

Replies (7)

RE: Problem while compiling my VERILOG-A code - Added by Wilson Snyder 11 months ago

Verilator doesn't support Verilog-A, nor does any other open source simulator I know of. Icarus Verilog has done some work towards Verilog-A, but I don't think it's escaped development yet.

RE: RE: Problem while compiling my VERILOG-A code - Added by Robert Szwarc 11 months ago

Ah ok. I thought in the standard 1364-2001 IEEE implemented real and tanh as well. Thank you for the information with Icarus Verilog. I will have a look to their page from time to time. I think I have read somewhere that adms works with Verilog-AMS but didn't try it yet. However, adms is not really a simulator. Adms translate Verilog-AMS to c-code and I think with this you can simulate your model but how I said I did not try it.

RE: Problem while compiling my VERILOG-A code - Added by Wilson Snyder 11 months ago

That's true, "real" is in 1364, though tanh is $tanh, that's a minor part of AMS though. Verilator however doesn't support real, though it probably will in about a month as it's almost working.

RE: RE: RE: Problem while compiling my VERILOG-A code - Added by Robert Szwarc 11 months ago

All right. Thank you for the information. I'll than look forward to the new version of verilator.

RE: Problem while compiling my VERILOG-A code - Added by Wilson Snyder 11 months ago

BTW if you can, feel free to post your example. No promises beyond we'll look at it. :)

RE: Problem while compiling my VERILOG-A code - Added by Robert Szwarc 10 months ago

Hi Wilson, I'm sorry for the late response but during the week I have not so much time. However I try to post the code tomorrow. Are there still some plans to implement Verilog-AMS ? I mean for semiconductor simulation it would be nice if you can use functions like ddx() for the calculation of the transconductance or capacitances.

RE: Problem while compiling my VERILOG-A code - Added by Wilson Snyder 10 months ago

No one including myself has expressed interest in contributing Verilog-AMS support code. (Excepting features also in SystemVerilog-2005 such as real.)

(1-7/7)