Verilator

I'm simulating a verilated verilog module in a SystemC test environment. The top level systemc provides a clock to the verilog module, which then divides the clock down and uses it to drive its internal logic as well as parts of the testbench. The attached diagram explains this better (sorry, couldn't get the image to appear inline).

The flop in Verilog (labeled V) works like it should. Its value is the value that flop D had in the previous cycle. However the flop in SystemC (labeled C) has exactly the same value as the flop D. In other words, C captures the value at the current cycle instead of the previous one. Is this a problem or is this to be expected given that there are two simulation "kernels" running (verilator and systemc)? Has anyone run into this sort of issue?

The workaround is to add a small delay at the input of C, but I'd rather not do that.

Thanks.