Verilator

Hi,

I'm new to verilator and I was wondering what a typical testbench looked like, in terms of language that it is written in and the structures and frameworks it uses. I come from a SystemVerilog/AVM/OBVM background, and used Vera before that, and behavioral VHDL and Verilog BFM-based testbenches before that, but I don't know where to start with writing a "proper" test suite to run verilated.

The examples seem to be more small testcases for the verilator system itself rather than a fully blown example, but please correct me if I'm wrong.

Jimbo