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Compiling verilog testbench
Added by Hui Chen 8 months ago
Hello Verilator developers,
I tried verilator-3.820 to compile verilog test benches. But I received some error messages, and I post some of them here: Unsupported: Verilog 1995 reserved word not implemented: wait syntax error, unexpected '@'
The second error message caused by the "repeat (1000) (posedge clk);" statement or " (posedge clk);"
Any suggestions for solving these errors?
Looking forward to your response.
Kind regards,
Hui
Replies (3)
RE: Compiling verilog testbench - Added by Hui Chen 8 months ago
The two error messages are 1) Unsupported: Verilog 1995 reserved word not implemented: wait 2) syntax error, unexpected '@'
The second error message caused by the "repeat (1000) (posedge clk);" statement or " (posedge clk);"
RE: Compiling verilog testbench - Added by Hui Chen 8 months ago
It seems as if the web did not display the '' mark correctly, if there are no quotes around it. The '' marks are not displayed before string " (posedge clk);" in the previous reply.
RE: Compiling verilog testbench - Added by Wilson Snyder 8 months ago
Verilator only supports synthesis constructs not testbenches, this is described under "Intro" and in the manual.
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