False BLKSEQ warning in case of a task call that occurs under the control of a clock edge

Dear developers:

I would like to inform you of a false BLKSEQ warning when I try to compile a tiny Verilog file (as attached) using Verilator-3.823.

Incidentally, I issued the following command: verilator --sc -Wall reverse_byte.v

The warning message can be found as below:

%Warning-BLKSEQ: test.v:34: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=). %Warning-BLKSEQ: Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message. %Error: Exiting due to 1 warning(s) %Error: Command Failed verilator_bin --sc -Wall test.v

Kind regards,

Hui Chen PhD student @TIMA Lab. | Visiting PhD student @NICTA

test.v (462 Bytes)

Replies (3)

RE: False BLKSEQ warning in case of a task call that occurs under the control of a clock edge - Added by Wilson Snyder 7 months ago

Thanks for the report. It just happens I think this was fixed yesterday in version 3.822.

RE: False BLKSEQ warning in case of a task call that occurs under the control of a clock edge - Added by Hui Chen 7 months ago

Dear Wilson,

Thank you very much for your prompt response. Yes, you are right. Nice job BTW ^_ (PS: it seems there is no version 3.822 in the repository)

King regards, Hui

RE: False BLKSEQ warning in case of a task call that occurs under the control of a clock edge - Added by Wilson Snyder 7 months ago

Due to a mistake the release was actually 3.823, which is the tag name that exists.

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