[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  Schedule::Load
  SVN::S4
  Synopsys-modes
  SystemPerl
  Verilog-Pli
  Voneline
  Vregs
General Info
  Papers

Calling $finish in an 'initial' section does not stop right away

Added by R. Diez 5 months ago

Hi all:

My simulation is doing some error checking in the "initial" section, and it's calling $display("Some error") and $finish because something is not quite right at the moment. However, that does not stop the "always @(posedge clk)" block from running once, which fails again, because some parameters were not correctly initialised (!).

Shouldn't Verilator stop trying to run the "always" block if the "initial" section calls $finish?

Thanks, R. Diez


Replies (1)

RE: Calling $finish in an 'initial' section does not stop right away - Added by Wilson Snyder 5 months ago

Try changing the code in V3EmitC.cpp so that the output code looks like this

 void Vtop::eval() {
    ...
    // Initialize
-    if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
+    if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) {
+        _eval_initial_loop(vlSymsp);
+        if (VL_UNLIKELY(Verilated::gotFinish())) return;
+    }

There still will be cases where other initials will get executed after the $finish, that won't be changed because the cost would be a test for finish at every block, which would be too slow.

(1-1/1)