Verilator

Hi all:

I have written the following piece of code for my upcoming OpenRISC Ethernet simulation model:

localparam buffer_descriptor_count = 128;
reg [31:0] buffer_descriptor_flags[ buffer_descriptor_count-1 : 0 ];

always @(posedge wb_clk_i)
begin
   if ( wb_rst_i )
     begin
        wb_dat_o <= 0;
        ...
...

for ( integer i = 0; i < buffer_descriptor_count; i++ )
  begin
     buffer_descriptor_flags[i] <= 0;
  end;

I am getting the BLKLOOPINIT error for the last "<=" assignment:

Unsupported: Delayed assignment to array inside for loops (non-delayed is ok - see docs)

If I change it to this:

buffer_descriptor_flags[i] = 0;

Then I get the following warning:

Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).

I think that, if Verilator forces you to use a blocking assignment, then it should not warn you that you should use a delay assignment instead.

Thanks, R. Diez