Verilator Parser (bison) as standalone parser for SystemVerilog files?

Hi,

I'm totally new to the Verilator but very impressed of what it can do! Thanks for all the hard work on it.

What I want to do, is create a UVM parser. My idea was to build it upon the Verilog/SystemVerilog parser within the Verilator. Do you think it is possible to use the parser and extend it to be a UVM parser? If yes, how :)

Thanks for every single reply!

Regards, pilzbug

Replies (5)

RE: Verilator Parser (bison) as standalone parser for SystemVerilog files? - Added by Wilson Snyder 4 months ago

Verilog-Perl has a complete SystemVerilog parser; see http://www.veripool.org/wiki/verilog-perl/Manual-verilog-perl#Verilog_Perl__which_parser_package

RE: Verilator Parser (bison) as standalone parser for SystemVerilog files? - Added by Jan Seyler 4 months ago

Hey,

thanks! This is great. And you can even extend it, because it is open source!

RE: Verilator Parser (bison) as standalone parser for SystemVerilog files? - Added by Jan Seyler 4 months ago

Is it possible to use Verilog::Parser in C/C++ and if it is possible, how can I do it? Any example would be great!

Thanks

RE: Verilator Parser (bison) as standalone parser for SystemVerilog files? - Added by Wilson Snyder 4 months ago

It's written in C++, so in theory yes, but there's no API, you'd have to dig in and make one yourself.

RE: Verilator Parser (bison) as standalone parser for SystemVerilog files? - Added by Jan Seyler 4 months ago

OK, I'll give it a try.

Thanks

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