Verilator

Hi all:

Sometimes it is handy to use a temporary variable like this:

int counter = 0;

always @(posedge clk)
  begin
     int tmp = counter + 1;  // Or something more complicated.
     $display( "New value: %d", tmp );  // Use tmp once.
     counter <= tmp;                    // Use tmp once again.
  end;

However, Verilator issues this warning for the temporary variable:

%Warning-BLKSEQ: /home/blah/blah.v:123: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).

Is there a way to prevent this warning without resorting to Verilator-specific pragmas in the source code?

Many thanks, R. Diez