verilated file use with commercial simulators in sv env
Can I use verilated DUT for simulation in a system verilog simulation environment in VCS/NCSIM/Modelsim? Maybe by using a DPI wrapper for the verilated DUT. My query is more on if at all I can do it? Please excuse if my query is too basic, as I did not find/understand a definite answer on above in FAQ's (I am a hardware engineer with a limited SW knowledge).
Yes, so long as you remember that the DUT will be 2-state (no X/Z) and generally following synthesis semantics. You can use DPI, or you can get Verilator to produce a SystemC model. I believe all three simulators you mention will co-simulate with SystemC.
I am trying yo use the verilated files converted to SystemC I'm trying to make it work on vcs mx and I am having errors, Do I need to use other setting or will it be like a pure systemc model only? I am new to systemc and also on running it on vcs, I am following the steps on vcs mx 1. syscan 2. vcs 3. simv Can you help me?, Thanks.