Verilator

This is a summary of what I've learned to do to simulate Xilinx projects using Verilator. Using the techniques described here I've been able to shorten simulation times from hours to minutes, although it can take a while (sometimes a few hours) to get the Xilinx unisims models into a form usable with Verilator.

First, the attached archive has everything required to exercise the MULT18X18S model including incorporating the GSR signal in glbl.

1. Extract the files from this archive
2. Copy the MULT18X18S.v file from the verilog/src/unisims directory in your distribution of ISE and then make the following modifications: (a) Add "// verilator tracing_off" as the line immediately following the "module" statement (this reduced the amount of garbage you'll get in your waveform files from Xilinx' models); (b) Delete the "tri0 GSR" line; (c) Change to two occurances of "GSR" to "glbl.GSR"; (d) Change the "p_out = 36'b0;" statement to "p_out <= 36'b0;"; and (e) Get rid of the "#100" delay in the subsequent assignment to "p_out". Note: If you don't make changes (b) through (e) you'll get warnings and/or errors from verilator. Try it and you'll see what happens when you try incorporating more of the Xilinx models required by real projects.
3. Type "make -f tb.mk"

1. The test bench in tb.v isn't a real project. It just requires one of Xilinx' unisims models so that glbl is required and the model has to be converted to a form usable by verilator. It also demonstrates a technique to generate stimuli to the model without requiring problematic "@ (posedge clk)" or "#xxx" delay statements inside an "initial" statement.
2. I haven't been able to successfully convert the Block RAM models provided with ISE. I gave up and put behavioral models in the code. In general, I avoid building Xilinx projects with behavioral models for large memories because I've seen 2 hour build times for projects that had taken 5 minutes total time because ISE required that much additional time to synthesize the large memory into discrete Block RAMs. I've also encountered cases where ISE did not infer a DSP48 primitive when one could be used, and have had to explicitely instantiate the DSP48 so as to get a faster clock.
3. I've been able to simulate the PicoBlaze processor using the provided Verilog source, although it took a couple of hours to resolve all the warnings and errors issued by Verilator about the original source code.