Verilog-Perl

Ahh, right. Thanks much for tracking down and making a patch; the only minor problem with it was that you were missing \n to terminate the symbol.

I pushed the fix to the git version, it'll be in 3.213. Let me know if you need it immediately.

BTW for next time please make a bug instead to aid my tracking; I filed bug106 and closed it.

I'm using version 3.301 and this still appears to be an issue. Here's what I'm seeing:

/****************************************************/
module pllcomp2bits (a, b, match, vcc);
input  vcc;
input [1:0] a, b;
output  match;

wire  \bit0 , bit1;

ah0non02ln0b5 \nor  (
    .a(\bit0 ),
    .b(bit1),
    .o1(match),
    .vcc(vcc)
);
ah0xon02ln0b0 xor0 (
    .a(a[0]),
    .b(b[0]),
    .o(\bit0 ),
    .vcc(vcc)
);
ah0xon02ln0b0 xor1 (
    .a(a[1]),
    .b(b[1]),
    .o(bit1),
    .vcc(vcc)
);
endmodule
/****************************************************/

Net \bit0 and instance name \nor are escaped.

# Perl snippet

my $nl = new Verilog::Netlist (options => $opt, link_read => $false, link_read_nonfatal => $true,);
$nl->read_file(filename => $opt_f);
$nl->link();
$nl->dump();

Output:

Module:pllcomp2bits  Kwd:module  File:/tmp/pllcomp2bits.v
  Port:a  Dir:in  DataT:[1:0]  Array:
  Port:b  Dir:in  DataT:[1:0]  Array:
  Port:match  Dir:out  DataT:  Array:
  Port:vcc  Dir:in  DataT:  Array:
  Net:a  O  DeclT:port  NetT:  DataT:[1:0]  Array:  1:0
  Net:b  O  DeclT:port  NetT:  DataT:[1:0]  Array:  1:0
  Net:bit0    DeclT:net  NetT:wire  DataT:  Array:
  Net:bit1    DeclT:net  NetT:wire  DataT:  Array:
  Net:match  I  DeclT:port  NetT:  DataT:  Array:
  Net:vcc  O  DeclT:port  NetT:  DataT:  Array:
  Cell:nor  is-a:ah0non02ln0b5
    Pin:a  Net:bit0
              Net:bit0    DeclT:net  NetT:wire  DataT:  Array:
    Pin:b  Net:bit1
              Net:bit1    DeclT:net  NetT:wire  DataT:  Array:
    Pin:o1  Net:match
              Net:match  I  DeclT:port  NetT:  DataT:  Array:
    Pin:vcc  Net:vcc
              Net:vcc  O  DeclT:port  NetT:  DataT:  Array:
  Cell:xor0  is-a:ah0xon02ln0b0
    Pin:a  Net:a[0]
    Pin:b  Net:b[0]
    Pin:o  Net:bit0
              Net:bit0    DeclT:net  NetT:wire  DataT:  Array:
    Pin:vcc  Net:vcc
              Net:vcc  O  DeclT:port  NetT:  DataT:  Array:
  Cell:xor1  is-a:ah0xon02ln0b0
    Pin:a  Net:a[1]
    Pin:b  Net:b[1]
    Pin:o  Net:bit1
              Net:bit1    DeclT:net  NetT:wire  DataT:  Array:
    Pin:vcc  Net:vcc
              Net:vcc  O  DeclT:port  NetT:  DataT:  Array:

Also when iterating over the netnames and cellnames within the module object, the escape character is not present.

Is there an option that preserves the escape character?

Thanks.

Dan

Oops sorry, no carriage returns.

module pllcomp2bits (a, b, match, vcc);

input  vcc;
input [1:0] a, b;
output  match;

wire  \bit0 , bit1;

ah0non02ln0b5 \nor  (
    .a(\bit0 ),
    .b(bit1),
    .o1(match),
    .vcc(vcc)
);

ah0xon02ln0b0 xor0 (
    .a(a[0]),
    .b(b[0]),
    .o(\bit0 ),
    .vcc(vcc)
);

ah0xon02ln0b0 xor1 (
    .a(a[1]),
    .b(b[1]),
    .o(bit1),
    .vcc(vcc)
);

endmodule

my $nl = new Verilog::Netlist (options => $opt, link_read => $false, link_read_nonfatal => $true,);

$nl->read_file(filename => $opt_f);

$nl->link();

$nl->dump();

Module:pllcomp2bits  Kwd:module  File:/tmp/pllcomp2bits.v
  Port:a  Dir:in  DataT:[1:0]  Array:
  Port:b  Dir:in  DataT:[1:0]  Array:
  Port:match  Dir:out  DataT:  Array:
  Port:vcc  Dir:in  DataT:  Array:
  Net:a  O  DeclT:port  NetT:  DataT:[1:0]  Array:  1:0
  Net:b  O  DeclT:port  NetT:  DataT:[1:0]  Array:  1:0
  Net:bit0    DeclT:net  NetT:wire  DataT:  Array:
  Net:bit1    DeclT:net  NetT:wire  DataT:  Array:
  Net:match  I  DeclT:port  NetT:  DataT:  Array:
  Net:vcc  O  DeclT:port  NetT:  DataT:  Array:
  Cell:nor  is-a:ah0non02ln0b5
    Pin:a  Net:bit0
              Net:bit0    DeclT:net  NetT:wire  DataT:  Array:
    Pin:b  Net:bit1
              Net:bit1    DeclT:net  NetT:wire  DataT:  Array:
    Pin:o1  Net:match
              Net:match  I  DeclT:port  NetT:  DataT:  Array:
    Pin:vcc  Net:vcc
              Net:vcc  O  DeclT:port  NetT:  DataT:  Array:
  Cell:xor0  is-a:ah0xon02ln0b0
    Pin:a  Net:a[0]
    Pin:b  Net:b[0]
    Pin:o  Net:bit0
              Net:bit0    DeclT:net  NetT:wire  DataT:  Array:
    Pin:vcc  Net:vcc
              Net:vcc  O  DeclT:port  NetT:  DataT:  Array:
  Cell:xor1  is-a:ah0xon02ln0b0
    Pin:a  Net:a[1]
    Pin:b  Net:b[1]
    Pin:o  Net:bit1
              Net:bit1    DeclT:net  NetT:wire  DataT:  Array:
    Pin:vcc  Net:vcc
              Net:vcc  O  DeclT:port  NetT:  DataT:  Array:

If a signal doesn't really need a \ escape, the escape is removed, this is necessary as "\foo " and "foo" must be the same signal.

The issue is really with the cell name "\nor ", (I just changed the bit0 to \bit0 to illustrate the removal of the identifier).

The cell name "nor" as opposed to "\nor " is the real issue, "nor" is a reserved keyword.

What I am attempting to do is identify and fix 1800-2005 reserved keywords. The netlister that I have is 1364-2001 compliant, but doesn't newer keywords, like "bind".

I'm using Verilog::Netlist to read in the netlist with Language set to 1364-2001. After parsing the netlist, I'm setting Language to 1800-2005 and using the Verilog::Language::is_keyword on the net names and cell names to identify what needs to be fixes.

I then plan on using vrename to fix the netlist to be 1800-2005 compliant.

With the removal of the escape character from the instance name "nor", this is not flagged as a keyword, whereas if it remained "\nor " it would not be flagged.

Am I making a Rube Goldberg contraption to solve something that is easily solved in another manner?

Ah, yes, not escaping keywords is a bug. I'll look at fixing it now.

Anyhow I suspect you can do what you want with vrename by adding a "--language" option (copy the option from vhier) then feeding in a rename list that shows every keyword like this:

"\bit "  "bit"

If you want, you could do it all in vrename by adding a flag that builds an internal rename list like this by foreach()ing over keywords in Verilog::Language.

Anyhow, please send back whatever you come up with, I'm sure it will come up again for others.

Here's my code and example input file

% rename_keywords -f pllcomp2bits.v

Issue above tracked in bug282.

I tried your suggestion and there is an issue. Since the "\" is dropped from the Netlist parser AND the vrename --list output, I don't know which items really need to be changed. So if I blindly rename any flagged keywords, the keywords which all ready have been escaped end up getting a double escape.

sigren   "bind"         "\bind " 
sigren   "bit"          "\bit " 
sigren   "nor"          "\nor " 

vrename --change --changefile signals.vrename pllcomp2bits.v

module pllcomp2bits (a, b, match, vcc);

input  vcc;
input [1:0] a, b;
output  match;

wire  \bind , \\bit  ;

ah0non02ln0b5 \\nor   (
    .a(\bind ),
    .b(\\bit  ),
    .o1(match),
    .vcc(vcc)
);

ah0xon02ln0b0 xor0 (
    .a(a[0]),
    .b(b[0]),
    .o(\bind ),
    .vcc(vcc)
);

ah0xon02ln0b0 xor1 (
    .a(a[1]),
    .b(b[1]),
    .o(\\bit  ),
    .vcc(vcc)
);

endmodule

I think that I see a workaround. Run "is_keyword" twice, first with 2001 and the second time with 2005. And then only change the items that are unique to the 2005 list. (this assumes that all 2001 keywords have been escaped all ready).

I think it's a bug that escaped names aren't preserved in vrename. Give me a few minutes...

Try the git version. I fixed the vrename issue, and while there, based on your keyword-in-one-but-not-the-other idea added the "vrename --changelang" option.

Got the git version:

- it clears up the vrename issue illustrated above. i.e. the double escapes issue is resolved.

- it clears up the issue with the parser (nl->dump) with the "\" being removed from escapes keywords, tested on both an escaped wire (\bit ) and instance name (\nor )

Hmmm, hopefully the new change to vrename will eliminate the need for my own wrapper script. But I may not have the usage just right:

% vrename --list --changelang --language 1364-2005 pll2to4dec.v
parse file pll2to4dec.v
Undefined subroutine &Verilog::Language::language_maximum called at /p/hsx/work/msv/msv_static/usr/bin/vrename line 308.

Works for me, perhaps you forgot to make install? If it still breaks, try "t/51_vrename_kwd.t", I added a test for it.

I installed, but the problem was competing Verilog-Perl installs on my system.

I had to add a "use lib <my_install_area>";" to the top of vrename while I get my DA team to upgrade their install (version 3.303+ ?).

Yes, it works with a two step process:

% vrename --list --changelang --language "1364-2005" /tmp/pll2to4dec.gates.v

% vrename --change /tmp/pll2to4dec.gates.v

Thanks so much.

Dan