Verilog-Perl

Verilog-Perl uses the standard Perl testing system, with all tests under the "t/" directory.

Most developers want to parse additional syntax, or have additional callbacks in the Verilog::SigParser. To test this it's easiest to just extend an existing test.

Create a little module with the syntax you want to support and put it at the bottom of verilog/parser_bugs.v. If appropriate, name the module with a bug number. Note there's also verilog/parser_sv.v which contains SystemVerilog code that isn't yet supported but is desirable to implement someday.

Run "make test", or the individual test with (for example) "t/35_sigparser.t". Running a test standalone will print more debugging information.

The t/35_sigparser.t test will parse verilog/parser_sv.v, and create test_dir/35.dmp. If you added additional code to verilog/parser_bugs.v the test will likely fail with unimplemented errors. Now's the time to fix the parser to support the new constructs.

When the parse errors have been fixed, the t/35_sigparser.t test will still fail, but with "%Warning: Line ... mismatches". This indicates a mismatch between comparing the test's output, test_dir/35.dmp, with the golden file t/35_sigparser.out. Manually verify the differences between the two files correspond correctly to what you'd expect from parsing whatever was added to new verilog/parser_bugs.v, then

cp test_dir/35.dmp t/35_sigparser.out

This will update the golden output and the test should now pass.